PROGRAMMABLE CLOCK GENERATOR 22 MARCH 10, 2017
5P49V5933 DATASHEET
Wiring the Differential Input to Accept Single-Ended Levels
Figure Recommended Schematic for Wiring a Differential
Input to Accept Single-ended Levels
shows how a differential
input can be wired to accept single ended levels. This
configuration has three properties; the total output impedance
of Ro and Rs matches the 50 ohm transmission line
impedance, the Vrx voltage is generated at the CLKIN inputs
which maintains the LVCMOS driver voltage level across the
transmission line for best S/N and the R1-R2 voltage divider
values ensure that Vrx p-p at CLKIN is less than the maximum
value of 1.2V.
Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
Table 24 Nominal Voltage Divider Values vs Driver VDD
shows resistor values that ensure the maximum drive level for
the CLKIN port is not exceeded for all combinations of 5%
tolerance on the driver VDD, the VersaClock Vddo_0 and 5%
resistor tolerances. The values of the resistors can be
adjusted to reduce the loading for slower and weaker
LVCMOS driver by increasing the impedance of the R1-R2
divider. To assist this assessment, the total load on the driver
is included in the table.
Table 24: Nominal Voltage Divider Values vs Driver VDD
HCSL Differential Clock Input Interface
CLKIN/CLKINB will accept DC coupled HCSL signals.
CLKIN, CLKINB Input Driven by an HCSL Driver
R1
R2
Vrx
VersaClock 5 Receiver
CLKI N
CLKI NB
LV CMOS
VDD
Zo = 50 Ohm
Ro + Rs = 50
Rs
Ro
LVCMOS Driver VDD Ro+Rs R1 R2 Vrx (peak) Ro+Rs+R1+R2
3.3 50.0 130 75 0.97 255
2.5 50.0 100 100 1.00 250
1.8 50.0 62 130 0.97 242
Zo=50ohm
Zo=50ohm
CLKIN
CLKINB
VersaClock 5 Receiver
Q
nQ
