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5P49V5933B000LTGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
MARCH 10, 2017 13 PROGRAMMABLE CLOCK GENERATOR
5P49V5933 DATASHEET
Table 19:Electrical Characteristics – DIF 0.7V Low Power HCSL Differential Outputs
(V
DDO
= 3.3V±5%, 2.5V±5%, TA = -40°C to +85°C)
1. Guaranteed by design and characterization. Not 100% tested in production.
2. Measured from differential waveform.
3. Slew rate is measured through the V
SWING
voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4. V
CROSS
is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge
(i.e. Clock rising and Clock# falling).
5. The total variation of all V
CROSS
measurements in any particular system. Note that this is a subset of V
CROSS
min/max (V
CROSS
absolute)
allowed. The intent is to limit V
CROSS
induced modulation by setting V
CROSS
to be smaller than V
CROSS
absolute.
6. Measured from single-ended waveform.
7. Measured with scope averaging off, using statistics function. Variation is difference between min. and max.
Symbol Parameter Conditions Min Typ Max Units Notes
dV/dt Slew Rate Scope averaging on 1 4 V/ns 1,2,3
Δ
dV/dt
Slew Rate Scope averaging on 20 % 1,2,3
VHIGH Voltage High 660 850 mV 1,6,7
VLOW Voltage Low -150 150 mV 1,6
VMAX Maximum Voltage 1150 mV 1
VMIN Minimum Voltage -300 mV 1
VSWING Voltage Swing
Scope averaging off
300 mV 1,2,6
VCROSS Crossing Voltage Value
Scope averaging off
250 550 mV 1,4,6
Δ
VCROSS
Crossing Voltage variation
Scope averaging off
140 mV 1,5
Statistical measurement on single-ended
signal using oscilloscope math function
(Scope averaging ON)
Measurement on single-ended signal using
absolute value (Scope averaging off)
PROGRAMMABLE CLOCK GENERATOR 14 MARCH 10, 2017
5P49V5933 DATASHEET
Table 20:AC Timing Electrical Characteristics
(V
DDO
= 3.3V+5% or 2.5V+5% or 1.8V ±5%, TA = -40°C to +85°C)
(Spread Spectrum Generation = OFF)
Symbol
Parameter Test Conditions
Min. Typ. Max. Units
fIN
1
Input Frequency
Input frequency limit (CLKIN, CLKINB)
1 350 MHz
Single ended clock output limit (LVCMOS)
1 200
Differential cock output limit (LVPECL/ LVDS/HCSL) 1 350
fVCO VCO Frequency
VCO operating frequency range
2600 2900 MHz
fPFD PFD Frequency
PFD operating frequency range 1
1
150 MHz
fBW Loop Bandwidth Input frequency = 25MHz 0.06 0.9 MHz
t2 Input Duty Cycle
Duty Cycle
45 50 55 %
Measured at VDD/2, all outputs except
Reference output OUT0, VDDOX = 2.5V or 3.3V
45 50 55 %
Measured at VDD/2, all outputs except
Reference output OUT0, VDDOX = 1.8V
40 50 60 %
Measured at VDD/2, Reference output
OUT0 (5MHz - 120MHz) with 50% duty cycle input
40 50 60 %
Measured at VDD/2, Reference output
OUT0 (150.1MHz - 200MHz) with 50% duty cycle input
30 50 70 %
Slew Rate, SLEW[1:0] = 00
1.0
2.2
Slew Rate, SLEW[1:0] = 01
1.2
2.3
Slew Rate, SLEW[1:0] = 10
1.3
2.4
Slew Rate, SLEW[1:0] = 11
1.7
2.7
Slew Rate, SLEW[1:0] = 00
0.6
1.3
Slew Rate, SLEW[1:0] = 01
0.7
1.4
Slew Rate, SLEW[1:0] = 10
0.6
1.4
Slew Rate, SLEW[1:0] = 11
1.0
1.7
Slew Rate, SLEW[1:0] = 00
0.3
0.7
Slew Rate, SLEW[1:0] = 01
0.4
0.8
Slew Rate, SLEW[1:0] = 10
0.4
0.9
Slew Rate, SLEW[1:0] = 11
0.7
1.2
Rise Times
LVDS, 20% to 80%
300
Fall Times
LVDS, 80% to 20%
300
Rise Times
LVPECL, 20% to 80%
400
Fall Times
LVPECL, 80% to 20%
400
fOUT Output Frequency
Single-ended 2.5V LVCMOS output clock rise and fall time, 20% to
80% of VDDO
(Output Load = 5 pF) VDDOX = 2.5V
Single-ended 1.8V LVCMOS output clock rise and fall time, 20% to
80% of VDDO
(Output Load = 5 pF) VDDOX=1.8V
MHz
t5 ps
t4
2
t3
5
Output Duty Cycle
Single-ended 3.3V LVCMOS output clock rise and fall time, 20% to
80% of VDDO
(Output Load = 5 pF) VDDOX = 3.3V
V/ns
MARCH 10, 2017 15 PROGRAMMABLE CLOCK GENERATOR
5P49V5933 DATASHEET
Cycle-to-Cycle jitter (Peak-to-Peak), multiple output frequencies
switching, differential outputs (1.8V to 3.3V nominal output voltage)
OUT0 = 25MHz
OUT1 = 100MHz
OUT2 = 125MHz
46 ps
Cycle-to-Cycle jitter (Peak-to-Peak), multiple output frequencies
switching, LVCMOS outputs (1.8 to 3.3V nominal output voltage)
OUT0 = 25MHz
OUT1 = 100MHz
OUT2 = 125MHz
74 ps
RMS Phase Jitter (12kHz to 5MHz
integration range) reference clock (OUT0),
25MHz LVCMOS outputs (1.8 to 3.3V nominal output voltage).
OUT0 = 25MHz
OUT1 = 100MHz
OUT2 = 125MHz
0.5 ps
(gg)
output, VDDO = 3.465V, 25MHz crystal, 156.25MHz output
frequency
OUT0 = 25MHz
OUT1 = 100MHz
OUT2 = 125MHz
0.75 1.5 ps
t7 Output Skew
Skew between the same frequencies, with outputs using the same
driver format and phase delay set to 0 ns.
75 ps
t8
3
Startup Time
PLL lock time from power-up, measured after all VDD's have raised
above 90% of their target value.
10 ms
t9
4
Startup Time PLL lock time from shutdown mode.
34ms
Initial frequency accuracy.
±2
Frequency stability over temperature.
±20
Aging per year.
±2
5. Duty Cycle is only guaranteed at max slew rate settings.
4. Actual PLL lock time depends on the loop configuration.
t6 Clock Jitter
2. A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
3. Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/write time.
ppmt10 Frequency Stability
1. Practical lower frequency is determined by loop filter settings.
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5P49V5933B000LTGI

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IDT
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Clock Generators & Support Products VersaClock 5 CLK Gen 350MHz 2 Input
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