OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

9FG1201HGLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
IDT
TM
/ICS
TM
Frequency Gearing Clock for
CPU, PCIe Gen1, Gen2, & FBD 1371F — 09/23/09
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
10
SMBusTable: Output Enable Readback Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
R X
Bit 6
R X
Bit 5
R X
Bit 4
R X
Bit 3
R X
Bit 2
R
X
Bit 1
R
X
Bit 0
R X
SMBusTable: Vendor & Revision ID Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
RID3
R
-
-
X
Bit 6
RID2
R
-
-
X
Bit 5
RID1
R
-
-
X
Bit 4
RID0 R - - X
Bit 3
VID3 R - - 0
Bit 2
VID2 R - - 0
Bit 1
VID1 R - - 0
Bit 0
VID0 R - - 1
SMBusTable: DEVICE ID
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
RW 1
Bit 6
RW 1
Bit 5
RW 0
Bit 4
RW
0
Bit 3
RW
0
Bit 2
RW
0
Bit 1
RW 0
Bit 0
RW 1
SMBusTable: Byte Count Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
BC7 RW - - 0
Bit 6
BC6 RW - - 0
Bit 5
BC5 RW - - 0
Bit 4
BC4 RW - - 0
Bit 3
BC3 RW - - 1
Bit 2
BC2 RW - - 0
Bit 1
BC1
RW
-
-
0
Bit 0
BC0 RW - - 1
Reserved
Device ID 2
Reserved
Device ID 1 Reserved
Reserved Readback
Readback - OE10_11# Input
Readback
Readback
Device ID 7 (MSB) Reserved
Readback - SMB_A2_PLLBYP# In Readback
Reserved Readback
Readback - OE8# Input
Readback
44
41
Device ID 6
Byte 6
-
-
Readback - OE9# Input
REVISION ID
-
-
30
53
Readback
Readback - HIGH_BW# In
-
-
VENDOR ID
-
-
-
1 Readback
46 Readback - FS_A_410
Byte 4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Byte 7
-
Byte 5
Writing to this register
configures how many
bytes will be read back.
Reserved
Device ID 5 Reserved
Device ID 4
Reserved
Device ID 3
Reserved
Device ID 0
IDT
TM
/ICS
TM
Frequency Gearing Clock for
CPU, PCIe Gen1, Gen2, & FBD 1371F — 09/23/09
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
11
SMBusTable: 1:1 PLL Frequency Selection
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
RW x
Bit 1
RW
1
Bit 0
RW Latch
SMBusTable: Reserved Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: M/N Programming Enable
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
M/N_EN
Gear PLL and 1:1 PLL
M/N Programming
Enable
RW Disable Enable 0
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
SMBus Table: Gear PLL Frequency Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
X
Bit 6
X
Bit 5
Gear PLL M Div5 RW X
Bit 4
Gear PLL M Div4 RW X
Bit 3
Gear PLL M Div3 RW X
Bit 2
Gear PLL M Div2 RW X
Bit 1
Gear PLL M Div1
RW
X
Bit 0
Gear PLL M Div0 RW X
RESERVED
RESERVED
See 9FG1201H M/N
programming Table
RESERVED
RESERVED
RESERVED
M Divider Programming
bits
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
See 9FG1201H 1:1 PLL
Programming Table
RESERVED
Frequency Select C
Frequency Select B
FS_A_410
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
-
-
-
-
Byte 8
-
RESERVED
Byte 11
-
-
-
-
Byte 10
-
RESERVED
RESERVED
RESERVED
RESERVED
Byte 9
IDT
TM
/ICS
TM
Frequency Gearing Clock for
CPU, PCIe Gen1, Gen2, & FBD 1371F — 09/23/09
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
12
SMBus Table: Gear PLL Frequency Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
Gear PLL N Div7 RW X
Bit 6
Gear PLL N Div6 RW X
Bit 5
Gear PLL N Div5 RW X
Bit 4
Gear PLL N Div4 RW X
Bit 3
Gear PLL N Div3 RW X
Bit 2
Gear PLL N Div2
RW
X
Bit 1
Gear PLL N Div1
RW
X
Bit 0
Gear PLL N Div0 RW X
SMBusTable: Gear PLL Output Divider Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
GoutDiv 3
RW
X
Bit 2
GoutDiv 2
RW
X
Bit 1
GoutDiv 1
RW
X
Bit 0
GoutDiv 1
RW
X
SMBusTable: Reserved Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBusTable: Reserved Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
RESERVED
RESERVED
RESERVED
Byte 15
Byte 13
Byte 14
-
RESERVED
RESERVED
RESERVED
RESERVED
See Gear Output Divider
Table
Gear Output Divider
RESERVED
N Divider Programming
bits
RESERVED
RESERVED
RESERVED
See 9FG1201H M/N
programming Table
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
-
-
-
Byte 12
-
-
-
-
RESERVED
RESERVED
RESERVED
RESERVED
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

9FG1201HGLFT

Mfr. #:
Buy 9FG1201HGLFT
Manufacturer:
Description:
Clock Buffer 12 Output PCIe Gearng Buffe
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet