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9FG1201HGLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
IDT
TM
/ICS
TM
Frequency Gearing Clock for
CPU, PCIe Gen1, Gen2, & FBD 1371F — 09/23/09
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
13
SMBusTable: Reserved Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: 1:1 PLL Frequency Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
1:1 PLL M Div5
RW
X
Bit 4
1:1 PLL M Div4 RW X
Bit 3
1:1 PLL M Div3 RW X
Bit 2
1:1 PLL M Div2 RW X
Bit 1
1:1 PLL M Div1 RW X
Bit 0
1:1 PLL M Div0 RW X
SMBus Table: 1:1 PLL Frequency Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
1:1 PLL N Div7 RW X
Bit 6
1:1 PLL N Div6 RW X
Bit 5
1:1 PLL N Div5 RW X
Bit 4
1:1 PLL N Div4
RW
X
Bit 3
1:1 PLL N Div3
RW
X
Bit 2
1:1 PLL N Div2
RW
X
Bit 1
1:1 PLL N Div1 RW X
Bit 0
1:1 PLL N Div0 RW X
SMBusTable: 1:1 PLL Output Divider Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
1outDiv 3
RW
X
Bit 2
1outDiv 2
RW
X
Bit 1
1outDiv 1
RW
X
Bit 0
1outDiv 1
RW
X
M Divider Programming
bits
-
-
Byte 16
Byte 17
-
-
-
-
Byte 18
-
-
-
-
-
-
-
Byte 19
-
RESERVED
RESERVED
RESERVED
N Divider Programming
bits
RESERVED
RESERVED
RESERVED
See 9FG1201H M/N
programming Table
RESERVED
RESERVED
RESERVED
1:1 Output Divider
See 1:1 Output Divider
Table
RESERVED
See 9FG1201H M/N
programming Table
RESERVED
RESERVED
RESERVED
RESERVED
IDT
TM
/ICS
TM
Frequency Gearing Clock for
CPU, PCIe Gen1, Gen2, & FBD 1371F — 09/23/09
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
14
SMBusTable: Reserved Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBusTable: Test Byte Register
Test
Type
PWD
Bit 7
RW
0
Bit 6
RW
0
Bit 5
RW
0
Bit 4
RW
0
Bit 3
RW
0
Bit 2
RW
0
Bit 1
RW
0
Bit 0
RW 0
Note: Do NOT write to Bit 21. Erratic device operation will result!
ICS ONLY TEST
Reserved
ICS ONLY TEST
Reserved
ICS ONLY TEST
Reserved
ICS ONLY TEST
Reserved
ICS ONLY TEST
Reserved
ICS ONLY TEST
Reserved
`
ICS ONLY TEST
Reserved
ICS ONLY TEST
Reserved
Byte 21
Test Function
RESERVED
RESERVED
Test Result
RESERVED
RESERVED
RESERVED
RESERVED
Byte 20
RESERVED
RESERVED
IDT
TM
/ICS
TM
Frequency Gearing Clock for
CPU, PCIe Gen1, Gen2, & FBD 1371F — 09/23/09
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
15
Absolute Max
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
3.3V Core Supply Voltage VDD_A GND - 0.5 V
DD
+ 0.5V V 1
3.3V Logic Supply Voltage VDD_In GND - 0.5 V
DD
+ 0.5V V 1
Storage Temperature Ts -65 150
°
C
1
Ambient Operating Temp Tambient 0 70 °C
1
Case Temperature Tcase 115 °C
1
Input ESD protection
ESD prot
Human Body Model
2000
V
1
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Input High Voltage V
IH
3.3 V +/-5%, Except CLK_IN 2 V
DD
+ 0.3 V 1
Input Low Voltage V
IL
3.3 V +/-5%, Except CLK_IN V
SS
- 0.3 0.8 V 1
Input High Current I
IH
V
IN
= V
DD
-5 5 uA
Input Low Current I
IL1
V
IN
= 0 V; Inputs with no pull-
up resistors
-5 uA
Low Threshold Input-
High Voltage
V
IH_FS
3.3 V +/-5%, Applies to
FS_A_410 pin
0.7 V
DD
+ 0.3 V 1
Low Threshold Input-
Low Voltage
V
IL_FS
3.3 V +/-5%, Applies to
FS_A_410 pin
V
SS
- 0.3 0.35 V 1
Operating Current I
DD3.3OP
all outputs driven 375 mA 1
Powerdown Current I
DD3.3PD
all differential pairs tri-stated 24 mA 1
Input Frequency F
i
V
DD
= 3.3 V 100 400 MHz 3
Pin Inductance L
pin
7 nH 1
C
IN
Logic Inputs 5 pF 1
C
OUT
Output pin capacitance 5 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up or de-
assertion of PD# to 1st clock
1.8 ms 1
Modulation Frequency Triangular Modulation 30 33 kHz 1
Tdrive_PD#
DIF output enable after
PD# de-assertion
300 us 1
Tfall_Pd#
PD# fall time of
5
ns
1
Trise_Pd#
PD# rise time of
5
ns
2
SMBus Voltage V
MAX
Maximum input voltage 5.5 V 1
Low-level Output Voltage V
OL
@ I
PULLUP
0.4 V 1
Current sinking at
V
OL
= 0.4 V
I
PULLUP
4 mA 1
SCLK/SDATA
Clock/Data Rise Time
T
RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000 ns 1
SCLK/SDATA
Clock/Data Fall Time
T
FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300 ns 1
Input Capacitance
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

9FG1201HGLFT

Mfr. #:
Buy 9FG1201HGLFT
Manufacturer:
Description:
Clock Buffer 12 Output PCIe Gearng Buffe
Lifecycle:
New from this manufacturer.
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