IDT
TM
/ICS
TM
Frequency Gearing Clock for
CPU, PCIe Gen1, Gen2, & FBD 1371F — 09/23/09
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
17
Electrical Characteristics - Skew and Differential Jitter Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
Group Parameter Description Min Typ Max Units Notes
CLK_IN, DIF[x:0]
t
SPO_PLL
Input-to-Output Skew in PLL mode (1:1 only),
CLK_IN, DIF[x:0]
t
PD_BYP
Input-to-Output Skew in Bypass mode (1:1 only),
CLK_IN, DIF [x:0]
∆t
SPO_PLL
Input-to-Output Skew Variation in PLL mode
(over specified voltage / temperature operating ranges)
CLK_IN, DIF [x:0]
∆t
PD_BYP
Input-to-Output Skew Variation in Bypass mode
(over specified voltage / temperature operating ranges)
Output-to-Output Skew Group of 2
(Common to Bypass and PLL mode)
10 25 ps 1,2,12
DIF[9:0]
t
SKEW_G10
Output-to-Output Skew Group of 10
(Common to Bypass and PLL mode)
40 50 ps 1,2,12
DIF[11:0]
t
SKEW_A12
Output-to-Output Skew across all 12 outputs (Common to
Bypass and PLL mode - all outputs at same gear)
80 100 ps 1,2,3,12
DIF[11:0]
t
JPH
Differential Phase Jitter (RMS Value) 5 10 ps 1,4,7,12
DIF[11:0]
t
SSTERROR
Differential Spread Spectrum Tracking Error (peak to peak) 40 80 ps 1,4,9,12
PLL Jitter Peaking
j
peak-hibw
(HIGH_BW# = 0) 0 2 2.5 dB 11,12
PLL Jitter Peaking
j
peak-lobw
(HIGH_BW# = 1) 0 1.3 2 dB 11,12
PLL Bandwidth
pll
HIBW
(HIGH_BW# = 0) 2 3.6 4 MHz 12,13
PLL Bandwidth
pll
LOBW
(HIGH_BW# = 1) 0.7 1.2 1.4 MHz 12,13
NOTES on Skew and Differential Jitter Parameters:
8. t is the period of the input clock
11.
Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
12. Guaranteed by design and characterization, not 100% tested in production.
13.
Measured at 3 db down or half power point.
1. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2. Measured from differential cross-point to differential cross-point
10. This parameter is an absolute value. It is not a double-sided figure.
9. Differential spread spectrum tracking error is the difference in spread spectrum tracking between two 9FG1201H devices This parameter is measured at the outputs of two
separate 9FG1201H devices driven by a single CK410B+ in Spread Spectrum mode. The 9FG1201H must set to high bandwidth. The spread spectrum characterisitics are :
maximum of 0.5%, 30 to 33KHz modulation frequency, linear profile.
5. Measured with scope averaging on to find mean value.
6. Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device.
7. This parameter is measured at the outputs of two separate 9FG1201H devices driven by a single CK410B+. The 9FG1201H must be set to high bandwidth. Differential
phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including the affects of spread spectrum). Target ranges of consideration are agents with
BW of 1-22MHz and 11-33MHz.
3. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4. This parameter is deterministic for a given device
