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X5325S8IZ-2.7A

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
7
FN8131.3
December 9, 2015
.
The watchdog timer bits, WD0 and WD1, select the
watchdog time out period. These nonvolatile bits are
programmed with the WRSR instruction.
The FLAG bit shows the status of a volatile latch that can be
set and reset by the system using the SFLB and RFLB
instructions. The flag bit is automatically reset upon
power-up. This flag can be used by the system to determine
whether a reset occurs as a result of a watchdog time out or
power failure.
Note: The Watch Dog Timer is shipped disabled. (WD1 = 1,
WD0 = 1. The factory default for Memory Block Protection is
‘None’. (BL1 = 0, BL0 = 0).
The nonvolatile WPEN bit is programmed using the WRSR
instruction. This bit works in conjunction with the WP
pin to
provide an in-circuit programmable ROM function (Table 2). WP
is LOW and WPEN bit programmed HIGH disables all status
register write operations.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and watchdog bits
from inadvertent corruption.
In the locked state (programmable ROM mode) the WP
pin is
LOW and the nonvolatile bit WPEN is “1”. This mode disables
nonvolatile writes to the device’s status register.
Setting the WP
pin LOW while WPEN is a “1” while an
internal write cycle to the status register is in progress will
not stop this write operation, but the operation disables
subsequent write attempts to the status register.
When WP
is HIGH, all functions, including nonvolatile writes
to the status register operate normally. Setting the WPEN bit
in the status register to “0” blocks the WP
pin function,
allowing writes to the status register when WP
is HIGH or
LOW. Setting the WPEN bit to “1” while the WP
pin is LOW
activates the programmable ROM mode, thus requiring a
change in the WP
pin prior to subsequent status register
changes. This allows manufacturing to install the device in a
system with WP
pin grounded and still be able to program
the status register. Manufacturing can then load
configuration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to be
protected by setting the block lock bits, and finally set the
“OTP mode” by setting the WPEN bit. Data changes now
require a hardware change.
Read Sequence
When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 16-bit address.
After the READ opcode and address are sent, the data
stored in the memory at the selected address is shifted out
on the SO line. The data stored in memory at the next
address can be read sequentially by continuing to provide
clock pulses. The address is automatically incremented to
the next higher address after each byte of data is shifted out.
STATUS
REGISTER BITS ARRAY ADDRESSES PROTECTED
BL1 BL0 X5323/X5325
0 0 None (factory default)
0 1 $0C00 to $0FFF
1 0 $0800 to $0FFF
1 1 $0000 to $0FFF
STATUS REGISTER BITS
WATCHDOG TIME-OUT
(TYPICAL)WD1 WD0
0 0 1.4s
0 1 600ms
1 0 200ms
1 1 disabled (factory default)
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
7 6543210
DATA OUT
CS
SCK
SI
SO
MSB
HIGH IMPEDANCE
INSTRUCTION
16-BIT ADDRESS
15 14 13 3 2 1 0
FIGURE 5. READ EEPROM ARRAY SEQUENCE
X5323, X5325
8
FN8131.3
December 9, 2015
When the highest address is reached, the address counter
rolls over to address $0000 allowing the read cycle to be
continued indefinitely. The read operation is terminated by
taking CS
high. Refer to the read EEPROM Array Sequence
(Figure 1).
To read the status register, the CS
line is first pulled low to
select the device followed by the 8-bit RDSR instruction.
After the RDSR opcode is sent, the contents of the status
register are shifted out on the SO line. Refer to the read
status register sequence (Figure 2).
Write Sequence
Prior to any attempt to write data into the device, the “Write
Enable” Latch (WEL) must first be set by issuing the WREN
instruction (Figure 3). CS
is first taken LOW, then the WREN
instruction is clocked into the device. After all eight bits of the
instruction are transmitted, CS
must then be taken HIGH. If
the user continues the write operation without taking CS
HIGH after issuing the WREN instruction, the write operation
will be ignored.
To write data to the EEPROM memory array, the user then
issues the WRITE instruction followed by the 16-bit address
and then the data to be written. Any unused address bits are
specified to be “0’s”. The WRITE operation minimally takes
32 clocks. CS
must go low and remain low for the duration of
the operation. If the address counter reaches the end of a
page and the clock continues, the counter will roll back to the
first address of the page and overwrite any data that may
have been previously written.
Note: When writing more than one page, you must wait one
write cycle (10ms typical) when going from one page to
another. This is required for the internal nonvolatile memory
to be programmed correctly.
For the page write operation (byte or page write) to be
completed, CS
can only be brought HIGH after bit 0 of the
last data byte to be written is clocked in. If it is brought HIGH
at any other time, the write operation will not be completed
(Figure 4).
To write to the status register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits 0 and
1 must be “0”.
While the write is in progress following a status register or
EEPROM Sequence, the status register may be read to
check the WIP bit. During this time the WIP bit will be high.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS
is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The write enable latch is reset.
• The flag bit is reset.
• Reset signal is active for t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• A WREN instruction must be issued to set the write enable
latch.
•CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
01234567891011121314
76543210
DATA OUT
CS
SCK
SI
SO
MSB
HIGH IMPEDANCE
INSTRUCTION
FIGURE 6. READ STATUS REGISTER SEQUENCE
X5323, X5325
9
FN8131.3
December 9, 2015
Symbol Table
01234567
CS
SI
SCK
HIGH IMPEDANCE
SO
FIGURE 7. WRITE ENABLE LATCH SEQUENCE
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
32 33 34 35 36 37 38 39
SCK
SI
CS
012345678910
SCK
SI
INSTRUCTION 16-BIT ADDRESS
DATA BYTE 1
76543210
CS
40 41 42 43 44 45 46 47
DATA BYTE 2
76543210
DATA BYTE 3
76543210
DATA BYTE N
15 14 13 3 2 1 0
20 21 22 23 24 25 26 27 28 29 30 31
654 321 0
FIGURE 8. WRITE SEQUENCE
0123456789
CS
SCK
SI
SO
HIGH IMPEDANCE
INSTRUCTION
DATA BYTE
765432 10
10 11 12 13 14 15
FIGURE 9. STATUS REGISTER WRITE SEQUENCE
X5323, X5325
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

X5325S8IZ-2.7A

Mfr. #:
Buy X5325S8IZ-2.7A
Manufacturer:
Renesas / Intersil
Description:
Supervisory Circuits CPU SUP/WDT 32K SPI EE RST HI 2 7-3 6V
Lifecycle:
New from this manufacturer.
Delivery:
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