IR3507PbF
Page 13 of 19 IR Confidential April 2, 2009
NOT RECOMMENDED FOR NEW DESIGNS
REPLACEMENT PRODUCT – IR3507ZPBF
PSI
PHSIN
GATEH
GATEL
A NTI-BIA S LA TCH
ENSURES GA TEH
TURNS ON FIRST
PSI DE-ASSERT
PSI ASSERT
Figure 7: PSI assertion and De-assertion
Debugging Mode
If CSIN+ pin is pulled up to VCCL voltage, IR3507 enters into debugging mode. Both drivers are pulled low and
IOUT output is disconnected from the current share bus, which isolates this phase IC from other phases.
However, the phase timing from PHSIN to PHSOUT does not change.
Emulated Bootstrap Diode
IR3507 integrates a PFET to emulate the bootstrap diode. If two or more top MOSFETs are to be driven at higher
switching frequency, an external bootstrap diode connected from VCCL pin to BOOST pin may be needed.
AFTER
OVP
FAULT
LATCH
130mV
OUTPUT
VOLTAGE
(VO)
OVP
THRESHOLD
VCCL-800 mV
OVP CONDITIONNORMAL OPERATION
IOUT(ISHARE)
GATEL
(PHASE IC)
GATEH
(PHASE IC)
VDAC
ERROR
AMPLIFIER
OUTPUT
(EAOUT)
Figure 8: Over-voltage protection waveforms
IR3507PbF
Page 14 of 19 IR Confidential April 2, 2009
NOT RECOMMENDED FOR NEW DESIGNS
REPLACEMENT PRODUCT – IR3507ZPBF
Over Voltage Protection (OVP)
The IR3507 includes over-voltage protection that turns on the low side MOSFET to protect the load in the event of a
shorted high-side MOSFET, converter out of regulation, or connection of the converter output to an excessive
output voltage. As shown in Figure 6, if IOUT pin voltage is above V(VCCL) – 0.8V, which represents over-voltage
condition detected by control IC, the over-voltage latch is set. GATEL drives high and GATEH drives low. The OVP
circuit overrides the normal PWM operation and within approximately 150ns will fully turn-on the low side MOSFET,
which remains ON until IOUT drops below V(VCCL) – 0.8V when over voltage ends. The over voltage fault is
latched in control IC and can only be reset by cycling the power to control IC. The error amplifier output (EAIN) is
pulled down by control IC and will remain low. The lower MOSFETs alone can not clamp the output voltage
however an SCR or N-MOSFET could be triggered with the OVP output to prevent processor damage.
Operation at Higher Output Voltage
The proper operation of the phase IC is ensured for output voltage up to 5.1V. Similarly, the minimum VCC for
proper operation of the phase IC is 8 V. Below this voltage, the current sharing performance of the phase IC is
affected.
DESIGN PROCEDURES - IR3507
Inductor Current Sensing Capacitor CCS and Resistor RCS
The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS and capacitor CCS
in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage across
the capacitor C
CS represents the inductor current. If the two time constants are not the same, the AC component of
the capacitor voltage is different from that of the real inductor current. The time constant mismatch does not affect the
average current sharing among the multiple phases, but does effect the current signal IOUT as well as the output
voltage during the load current transient if adaptive voltage positioning is adopted.
Measure the inductance L and the inductor DC resistance R
L. Pre-select the capacitor CCS and calculate RCS as
follows.
CS
L
CS
C
RL
R =
(1)
Bootstrap Capacitor CBST
Depending on the duty cycle and gate drive current of the phase IC, a capacitor in the range of 0.1uF to 1uF is
needed for the bootstrap circuit.
Decoupling Capacitors for Phase IC
A 0.1uF-1uF decoupling capacitor is required at the VCCL pin.
CURRENT SHARE LOOP COMPENSATION
The internal compensation of current share loop ensures that crossover frequency of the current share loop is at least
one decade lower than that of the voltage loop so that the interaction between the two loops is eliminated. The
crossover frequency of current share loop
is approximately 8 kHz.
IR3507PbF
Page 15 of 19 IR Confidential April 2, 2009
NOT RECOMMENDED FOR NEW DESIGNS
REPLACEMENT PRODUCT – IR3507ZPBF
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout; therefore, minimizing the noise coupled to the IC.
Dedicate at least one middle layer for a ground plane.
Separate analog bus (EAIN, DACIN, and IOUT) from digital bus (CLKIN, PSI, PHSIN, and PHSOUT) to reduce
the noise coupling.
Connect PGND to LGND pins of each phase IC to the ground tab, which is tied to PGND planes respectively
through vias.
Place current sense resistors and capacitors (R
CS and CCS) close to phase IC. Use Kelvin connection for the
inductor current sense wires, but separate the two wires by ground polygon or as differential routing. The wire
from the inductor terminal to CSIN- should not cross over the fast transition nodes, i.e., switching nodes, gate
drive outputs, and bootstrap nodes.
Place the decoupling capacitors C
VCC and CVCCL as close as possible to VCC and VCCL pins of the phase IC
respectively.
Place the phase IC as close as possible to the MOSFETs to reduce the parasitic resistance and inductance of
the gate drive paths.
Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET. Use
combination of different packages of ceramic capacitors.
There are two switching power loops. One loop includes the input capacitors, top MOSFET, inductor, output
capacitors and the load; another loop consists of bottom MOSFET, inductor, output capacitors and the load.
Route the switching power paths using wide and short traces or polygons; use multiple vias for connections
between layers.

IR3507MTRPBF

Mfr. #:
Manufacturer:
Infineon / IR
Description:
Power Management Specialized - PMIC XPHASE3 DDR VTT 7V 2A 3 Wire
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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