IR3507PbF
Page 8 of 19 IR Confidential April 2, 2009
NOT RECOMMENDED FOR NEW DESIGNS
REPLACEMENT PRODUCT – IR3507ZPBF
Frequency and Phase Timing Control
The oscillator is located in the Control IC and the system clock frequency is programmable from 250kHz to 9MHZ by an
external resistor. The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase
timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output (PHSOUT) is
connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to
PHSIN of the second phase IC, etc. and PHSOUT of the last phase IC is connected back to PHSIN of the control IC.
During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects the
feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 2 shows the
phase timing for a four phase converter. The switching frequency is set by the resistor ROSC. The clock frequency
equals the number of phase times the switching frequency.
Phase IC1
PWM Latch SET
Control IC CLKOUT
(Phase IC CLKIN)
Control IC PHSOUT
(Phase IC1 PHSIN)
Phase IC 1 PHSOUT
(Phase IC2 PHSIN)
Phase IC 2 PHSOUT
(Phase IC3 PHSIN)
Phase IC 3 PHSOUT
(Phase IC4 PHSIN)
Phase IC4 PHSOUT
(Control IC PHSIN)
Figure 2: Four Phase Oscillator Waveforms
PWM Operation
The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock pulse, the PWM latch is set;
the PWMRMP voltage begins to increase; the low side driver is turned off, and the high side driver is then turned on
after the non-overlap time. When the PWMRMP voltage exceeds the error amplifier’s output voltage, the PWM latch is
reset. This turns off the high side driver and then turns on the low side driver after the non-overlap time; it activates the
ramp discharge clamp, which quickly discharges the PWMRMP capacitor to the output voltage of share adjust amplifier
in phase IC until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode input
range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement
guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors
response to a load step decrease, which is appropriate given the low output to input voltage ratio of most systems. The
inductor current will increase much more rapidly than decrease in response to load transients. The error amplifier is a
high speed amplifier with 110 dB of open loop gain. It is not unity gain stable. This control method is designed to provide
“single cycle transient response” where the inductor current changes in response to load transients within a single
switching cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements.
