IR3507PbF
Page 4 of 19 IR Confidential April 2, 2009
NOT RECOMMENDED FOR NEW DESIGNS
REPLACEMENT PRODUCT – IR3507ZPBF
PARAMETER TEST CONDITION MIN TYP MAX UNIT
PWM Comparator
PWM Ramp Slope Vin=12V 42 52.5 57 mV/
%DC
Input Offset Voltage Note 1 -5 0 5 mV
EAIN Bias Current 0 EAIN 3V -5 -0.3 5
µA
Minimum Pulse Width Note 1 55 70 ns
Minimum GATEH Turn-off
Time
20 80 160 ns
Current Sense Amplifier
CSIN+/- Bias Current -200 0 200 nA
CSIN+/- Bias Current
Mismatch
Note 1 -50 0 50 nA
Input Offset Voltage CSIN+ = CSIN- = DACIN. Measure
input referred offset from DACIN
-1 0 1 mV
Gain 0.5V V(DACIN) < 1.6V 30.0 32.5 35.0 V/V
Unity Gain Bandwidth C(IOUT)=10pF. Measure at IOUT.
Note 1
4.8 6.8 8.8 MHz
Slew Rate 6
V/µs
Differential Input Range 0.8V V(DACIN) 1.6V, Note 1 -10 50 mV
Differential Input Range 0.5V V(DACIN) < 0.8V, Note 1 -5 50 mV
Common Mode Input Range Note 1 0 Note2 V
Rout at T
J
= 25
o
C Note 1 2.3 3.0 3.7 k
Rout at T
J
= 125
o
C 3.6 4.7 5.4 k
IOUT Source Current 0.5 1.6 2.9 mA
IOUT Sink Current 0.5 1.4 2.9 mA
Share Adjust Amplifier
Input Offset Voltage Note 1 -3 0 3 mV
Differential Input Range Note 1 -1 1 V
Gain CSIN+ = CSIN- = DACIN. Note 1 4 5.0 6 V/V
Unity Gain Bandwidth Note 1 4 8.5 17 kHz
PWM Ramp Floor Voltage IOUT Open, Measure relative to DACIN -116 0 116 mV
Maximum PWM Ramp Floor
Voltage
IOUT = DACIN – 200mV. Measure
relative to floor voltage.
120 180 240 mV
Minimum PWM Ramp Floor
Voltage
IOUT = DACIN + 200mV. Measure
relative to floor voltage.
-220 -160 -100 mV
PSI Comparator
Rising Threshold Voltage Note 1 520 620 700 mV
Falling Threshold Voltage Note 1 400 550 650 mV
Hysteresis Note 1 50 70 120 mV
Resistance 200 500 850 k
Floating Voltage 800 1150 mV
IR3507PbF
Page 5 of 19 IR Confidential April 2, 2009
NOT RECOMMENDED FOR NEW DESIGNS
REPLACEMENT PRODUCT – IR3507ZPBF
Note 1: Guaranteed by design, but not tested in production
Note 2: V
CCL
-0.5V or V
CC
– 2.5V, whichever is lower
PARAMETER TEST CONDITION MIN TYP MAX UNIT
Body Brake Comparator
Threshold Voltage with EAIN
decreasing
Measure relative to Floor Voltage -300 -200 -110 mV
Threshold Voltage with EAIN
increasing
Measure relative to Floor Voltage -200 -100 -10 mV
Hysteresis 70 105 130 mV
Propagation Delay VCCL = 5V. Measure time from EAIN <
V(DACIN) (200mV overdrive) to GATEL
transition to < 4V.
40 65 90 ns
OVP Comparator
OVP Threshold Step V(IOUT) up until GATEL drives
high. Compare to V(VCCL)
-1.0 -0.8 -0.4 V
Propagation Delay V(VCCL)=5V, Step V(IOUT) up from
V(DACIN) to V(VCCL). Measure time to
V(GATEL)>4V.
15 40 70 ns
Synchronous Rectification Disable Comparator
Threshold Voltage The ratio of V(CSIN-) / V(DACIN), below
which V(GATEL) is always low.
66 75 86 %
Negative Current Comparator
Input Offset Voltage Note 1 -16 0 16 mV
Propagation Delay Time Apply step voltage to V(CSIN+) –
V(CSIN-). Measure time to V(GATEL)<
1V.
100 200 400 ns
Bootstrap Diode
Forward Voltage I(BOOST) = 30mA, VCCL = 6.8V 360 520 960 mV
Debug Comparator
Threshold Voltage Compare to V(VCCL) -250 -150 -50 mV
General
VCC Supply Current 8V V(VCC) < 10V 1.1 4.0 6.1 mA
VCC Supply Current 10V V(VCC) 16V 1.1 2.0 4 mA
VCCL Supply Current 3.1 8.0 12.1 mA
BOOST Supply Current 4.75V V(BOOST)-V(SW ) 8V 0.5 1.5 3 mA
DACIN Bias Current -1.5 -0.75 1
µA
SW Floating Voltage 0.1 0.3 0.4 V
IR3507PbF
Page 6 of 19 IR Confidential April 2, 2009
NOT RECOMMENDED FOR NEW DESIGNS
REPLACEMENT PRODUCT – IR3507ZPBF
PIN DESCRIPTION
PIN# PIN SYMBOL PIN DESCRIPTION
1 IOUT Output of the Current Sense Amplifier is connected to this pin through a 3k
resistor. Voltage on this pin is equal to V(DACIN) + 33 [V(CSIN+) – V(CSIN-)].
Connecting all IOUT pins together creates a share bus which provides an indication
of the average current being supplied by all the phases. The signal is used by the
Control IC for voltage positioning and over-current protection. OVP mode is initiated
if the voltage on this pin rises above V(VCCL)- 0.8V.
2 PSI Logic low is an active low (IE low=low power state).
3 DACIN Reference voltage input from the Control IC. The Current Sense signal and PWM
ramp is referenced to the voltage on this pin.
4 LGND Ground for internal IC circuits. IC substrate is connected to this pin.
5 PHSIN Phase clock input.
6 NC N/A
7 PHSOUT Phase clock output.
8 CLKIN Clock input.
9 PGND Return for low side driver and reference for GATEH non-overlap comparator.
10 GATEL Low-side driver output and input to GATEH non-overlap comparator.
11 NC N/A
12 VCCL Supply for low-side driver. Internal bootstrap synchronous PFET is connected from
this pin to the BOOST pin.
13 BOOST Supply for high-side driver. Internal bootstrap synchronous PFET is connected
between this pin and the VCCL pin.
14 GATEH High-side driver output and input to GATEL non-overlap comparator.
15 SW Return for high-side driver and reference for GATEL non-overlap comparator.
16 VCC Supply for internal IC circuits.
17 CSIN+ Non-Inverting input to the current sense amplifier, and input to debug comparator.
18 CSIN- Inverting input to the current sense amplifier, and input to synchronous rectification
disable comparator.
19 EAIN PWM comparator input from the error amplifier output of Control IC. Body Braking
mode is initiated if the voltage on this pin is less than V(DACIN).
20 NC N/A

IR3507MTRPBF

Mfr. #:
Manufacturer:
Infineon / IR
Description:
Power Management Specialized - PMIC XPHASE3 DDR VTT 7V 2A 3 Wire
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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