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AD7225LPZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
AD7225
Rev. C | Page 12 of 24
SPECIFICATION RANGES
For the AD7225 to operate to rated specifications, its input
reference voltage must be at least 4 V below the V
DD
power
supply voltage. This voltage differential is the overhead voltage
required by the output amplifiers.
The AD7225 is specified to operate over a V
DD
range from 12 V
± 5% to 15 V ± 10% (that is, from 11.4 V to 16.5 V) with a V
SS
of −5 V ± 10%. Operation is also specified for a single 15 V ±
5% V
DD
supply. Applying a V
SS
of −5 V results in improved zero-
code error, improved output sink capability with outputs near
AGND, and improved negative-going settling time.
Performance is specified over a wide range of reference voltages
from 2 V to (V
DD
− 4 V) with dual supplies. This allows a range
of standard reference generators to be used, such as the AD780,
a 2.5 V band gap reference, and the AD584, a precision 10 V
reference. Note that an output voltage range of 0 V to 10 V
requires a nominal 15 V ± 5% power supply voltage.
AD7225
Rev. C | Page 13 of 24
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for each channel of the
AD7225, with the output voltage having the same positive
polarity as V
REF
x. The AD7225 can be operated single supply
(V
SS
= AGND) or with positive/negative supplies (see the Op
Amp Section, which outlines the advantages of having negative
V
SS
). Connections for the unipolar output operation are shown
in Figure 16. The voltage at any of the reference inputs must
never be negative with respect to DGND. Failure to observe this
precaution may cause parasitic transistor action and possible
device destruction. The code table for unipolar output
operation is shown in Table 7.
Note,
( )
( )
==
−
256
1
21
8
REFREF
VVLSB
V
REF
A V
REF
B V
REF
C V
REF
D V
DD
V
SS
AGND DGND
V
OUT
A
DAC A
V
OUT
B
DAC B
V
OUT
C
DAC C
V
OUT
D
DAC D
DB7
(MSB)
DB0
(LSB)
A1
A2
WR
LDAC
AD7225
00986-016
Figure 16. Unipolar Output Circuit
Table 7. Unipolar Code Table
DAC Latch Contents
Analog Output
MSB LSB
1111 1111
( )
256
255
REF
V+
1000 0001
( )
256
129
REF
V+
1000 0000
( )
2
256
128
REF
REF
V
V +=+
0111 1111
( )
256
127
REF
V+
0000 0001
( )
256
1
REF
V+
0000 0000 0 V
AD7225
Rev. C | Page 14 of 24
BIPOLAR OUTPUT OPERATION
Each of the DACs of the AD7225 can be individually confi-
gured to provide bipolar output operation. This is possible
using one external amplifier and two resistors per channel.
Figure 17 shows a circuit used to implement offset binary
coding (bipolar operation) with DAC A (DAC Channel A)
of the AD7225. In this case,
( ) ( )
REFREF
A
OUT
V
R
R2
VD
R1
R2
V ×
−×
+=
1
1
With R1 = R2
( )
( )
REF
A
OUT
VDV
×−=
12
where D
A
is a fractional representation of the digital word in
Latch A (0 ≤ D
A
≤ 255/256).
Mismatch between R1 and R2 causes gain and offset errors and,
therefore, these resistors must match and track over tempera-
ture. The AD7225 can be operated in single supply or from
positive/negative supplies. Table 8 shows the digital code vs.
output voltage relationship for the circuit of Figure 17 with
R1 = R2.
+15V
–15V
V
DD
V
SS
AGND DGND
V
OUT
A
DAC A
AD7225*
V
REF
A
R2
V
OUT
R1
V
REF
R1, R2 = 10kΩ ± 0.1%.
*DIGITAL INPUTS OMITTED
FOR CLARITY.
00986-017
Figure 17. Bipolar Output Circuit
Table 8. Bipolar (Offset Binary) Code Table
DAC Latch Contents
Analog Output MSB LSB
1111 1111
( )
128
127
REF
V+
1000 0001
( )
128
1
REF
V+
1000 0000 0 V
0111 1111
( )
128
1
REF
V−
0000 0001
( )
128
127
REF
V−
0000 0000
( )
REFREF
VV −=− 1
128
128
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD7225LPZ-REEL

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Digital to Analog Converters - DAC CMOS QUAD 8 BIT V-OUT IC
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