AD7225
Rev. C | Page 18 of 24
less, there exists a good correlation with the actual performance
of the transversal filter (see Figure 23).
DIGITAL WORD MULTIPLICATION
Because each DAC of the AD7225 has a separate reference input,
the output of one DAC can be used as the reference input for
another. This means that multiplication of digital words can be
performed (with the result given in analog form). For example,
if the output from DAC A is applied to V
REF
B, then the output
from DAC B, V
OUT
B, can be expressed as:
V
OUT
B = D
A
× D
B
× V
REF
A
where D
A
and D
B
are the fractional representations of the digital
words in DAC Latch A and DAC Latch B, respectively.
If D
A
= D
B
= D, the result is D
2
× V
REF
A.
In this manner, the four DACs can be used on their own or in
conjunction with an external summing amplifier to generate
complex waveforms. Figure 24 shows one such application.
In this case, the output waveform, Y, is represented by
Y = −(x
4
+ 2x
3
+ 3x
2
+ 2x + 4) × V
IN
where x is the digital code that is applied to all four DAC
latches.
*DIGITAL INPUTS OMITTED FOR CLARITY.
100k
Y
V
OUT
AV
REF
A
V
OUT
BV
REF
B
V
OUT
CV
REF
C
V
OUT
D
V
REF
D
V
SS
AGND
DGND
15V
V
DD
AD7225*
V
IN
100k
50k
33k
50k
25k
00986-024
Figure 24. Complex Waveform Generation
AD7225
Rev. C | Page 19 of 24
MICROPROCESSER INTERFACE
*LINEAR CIRCUITRY OMITTED FOR CLARITY.
ADDRESS
DECODE
LATCH
EN
AD7225*
A0
A1
DB7
DB0
LDAC
WR
ADDRESS BUS
ADDRESS DATA BUS
8085A/
8088
A15
A8
ALE
AD0
AD7
WR
00986-025
*LINEAR CIRCUITRY OMITTED FOR CLARITY.
Z-80
A15
A8
D0
D7
AD7225*
WR
A0
A1
DB7
DB0
LDAC
WR
ADDRESS BUS
DATA BUS
ADDRESS
DECODE
EN
MREQ
00986-026
Figure 25. AD7225-to-8085A/8088 Interface, Double-Buffered Mode Figure 26. AD7225-to-Z-80 Interface, Double-Buffered Mode
*LINEAR CIRCUITRY OMITTED FOR CLARITY.
6809/
6502
A15
A0
E OR Φ2
D0
D7
AD7225*
R/W
A0
A1
DB7
DB0
LDAC
WR
ADDRESS BUS
DATA BUS
ADDRESS
DECODE
EN
00986-027
*LINEAR CIRCUITRY OMITTED FOR CLARITY.
68008
A23
A1
D0
D7
AD7225*
A0
A1
DB7
DB0
LDAC
WR
ADDRESS BUS
DATA BUS
ADDRESS
DECODE
EN
AS
R/W
DTACK
00986-028
Figure 27. AD7225-to-6809/6502 Interface, Single-Buffered Mode Figure 28. AD7225-to-68008 Interface, Single-Buffered Mode
AD7225
Rev. C | Page 20 of 24
V
SS
GENERATION
Operating the AD7225 from dual supplies results in enhanced
performance over single-supply operation on a number of
parameters as previously outlined. Some applications may
require this enhanced performance, but may only have a single
power supply rail available. The circuit of Figure 29 shows a
method of generating a negative voltage using one CD4049,
operated from a V
DD
of 15 V. Two inverters of the hex inverter
chip are used as an oscillator. The other four inverters are in
parallel and used as buffers for higher output current. The
square wave output is level translated to a negative-going signal,
then rectified and filtered. The circuit configuration shown
provides an output voltage of 5.1 V for current loadings in the
range of 0.5 mA to 9 mA. This satisfies the AD7225 I
SS
require-
ment over the commercial operating temperature range.
1/6
CD4049AE
1/6
CD4049AE
1/6
CD4049AE
1/6
CD4049AE
1/6
CD4049AE
1/6
CD4049AE
510k
5.1k
+
0.02µF
47µF
47µF 5V1
–V
OUT
+
+
1N4001
1N4001
510
00986-029
Figure 29. V
SS
Generation Circuit

AD7225LPZ-REEL

Mfr. #:
Manufacturer:
Description:
Digital to Analog Converters - DAC CMOS QUAD 8 BIT V-OUT IC
Lifecycle:
New from this manufacturer.
Delivery:
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