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AD7225LPZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
AD7225
Rev. C | Page 6 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
OUT
B
1
V
OUT
A
2
V
SS
3
V
REF
B
4
V
OUT
C
24
V
OUT
D
23
V
DD
22
V
REF
C
21
V
REF
A
5
V
REF
D
20
AGND
6
A0
19
DGND
7
A1
18
LDAC
8
WR
17
DB7
9
DB0
16
DB6
10
DB1
15
DB5
11
DB2
14
DB4
12
DB3
13
AD7225
TOP VIEW
(Not to Scale)
00986-002
1 28 27 26234
5
6
7
8
9
10
11
25
24
23
22
21
20
19
NC = NO CONNECT
V
REF
B
V
REF
A
AGND
NC
DGND
LDAC
DB7
V
REF
C
V
REF
D
A0
NC
A1
WR
DB0
V
SS
V
OUT
A
V
OUT
B
NC
V
OUT
C
V
OUT
D
V
DD
DB6
DB5
DB4
NC
DB3
DB2
DB1
PIN 1
INDENTFIER
12 13 14 15 16 17 18
AD7225
TOP VIEW
(Not to Scale)
00986-003
Figure 2. PDIP, SOIC, CERDIP, and SSOP Figure 3. PLCC
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
PDIP, SOIC,
CERDIP, SSOP
PLCC
1 2 V
OUT
B DAC Channel B Voltage Output.
2 3 V
OUT
A DAC Channel A Voltage Output.
3 4 V
SS
Negative Power Supply Connection.
4 5 V
REF
B Reference Voltage Connection for DAC Channel B.
5 6 V
REF
A Reference Voltage Connection for DAC Channel A.
6 7 AGND Analog Ground Reference Connection.
7 9 DGND Digital Ground Reference Connection.
8 10
LDAC Active Low Load DAC Signal. DAC register data is latched on the rising edge of LDAC.
9 11 DB7 Data Bit 7 (Most Significant Data Bit).
10 12 DB6 Data Bit 6.
11 13 DB5 Data Bit 5.
12 14 DB4 Data Bit 4.
13 16 DB3 Data Bit 3.
14 17 DB2 Data Bit 2.
15 18 DB1 Data Bit 1.
16 19 DB0 Data Bit 0 (Least Significant Data Bit).
17 20
WR Active Low Data Write Signal. Input register data is latched on the rising edge of WR.
18 21 A1 DAC Address Select Pin.
19 23 A0 DAC Address Select Pin.
20 24 V
REF
D Reference Voltage Connection for DAC Channel D.
21 25 V
REF
C Reference Voltage Connection for DAC Channel C.
22 26 V
DD
Positive Power Supply Connection.
23 27 V
OUT
D DAC Channel D Voltage Output.
24 28 V
OUT
C DAC Channel C Voltage Output.
N/A 1, 8, 15, 22 NC No Internal Connection.
AD7225
Rev. C | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
T
A
= 25°C, V
DD
= 15 V, V
SS
= −5 V, unless otherwise noted.
Figure 4. Channel-to-Channel Matching
1.0
–1.0
–0.5
0
0.5
0 1 2 3 4 5 6 7 8 9 10 11 12 13
RELATIVE ACCURACY (LSB)
V
REF
(V)
V
DD
= 5V V
DD
= 12V V
DD
= 15V
00986-005
Figure 5. Relative Accuracy vs. V
REF
0.50
–0.50
–0.25
0
0.
25
0 1 2 3 4 5 6 7 8 9 10 11 12 13
DIFFERENTIAL NONLINEARITY (LSB)
V
REF
(V)
V
DD
= 5V V
DD
= 12V V
DD
= 15V
00986-006
Figure 6. Differential Nonlinearity vs. V
REF
8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
7
–60 –40 –20 0 20 40 60 80 100 120 140
POWER SUPPLY CURRENT (mA)
TEMPERATURE (°C)
I
DD
I
SS
00986-007
Figure 7. Power Supply Current vs. Temperature
5
–5
–4
–3
–2
–1
0
1
2
3
4
–60 –40 –20 0 20 40 60 80 100 120 140
ZERO CODE ERROR (mV)
TEMPERATURE (°C)
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
00986-008
Figure 8. Zero Code Error vs. Temperature
100
90
10
0%
1ms/DIV
300µV
00986-009
Figure 9. Broadband Noise
AD7225
Rev. C | Page 8 of 24
TERMINOLOGY
Total Unadjusted Error
Tota l unadjusted error is a comprehensive specification that
includes full-scale error, relative accuracy, and zero code error.
Maximum output voltage is V
REF
− 1 LSB (ideal), where 1 LSB
(ideal) is V
REF
/256. The LSB size varies over the V
REF
range.
Therefore, the zero code error, relative to the LSB size, increases
as V
REF
decreases. Accordingly, the total unadjusted error, which
includes the zero code error, also varies in terms of LSB over the
V
REF
range. As a result, total unadjusted error is specified for a
fixed reference voltage of 10 V.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
allowing for zero code error and full-scale error and is normally
expressed in LSB or as a percentage of full-scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
over the operating temperature range ensures monotonicity.
Digital Feedthrough
Digital feedthrough is the glitch impulse transferred to the
output of the DAC due to a change in its digital input code. It is
specified in nV sec and is measured at V
REF
= 0 V.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one converter (not addressed) due to a change in the digital
input code to another addressed converter. It is specified in nV
sec and is measured at V
REF
= 0 V.
AC Feedthrough
AC feedthrough is the proportion of reference input signal that
appears at the output of a converter when that DAC is loaded
with all 0s.
Channel-to-Channel Isolation
Channel-to-channel isolation is the proportion of input signal
from the reference of one DAC (loaded with all 1s) that appears
at the output of one of the other three DACs (loaded with all 0s)
The figure given is the worst case for the three other outputs
and is expressed as a ratio in dB.
Full-Scale Error
Full-scale error is defined as
FSE = Measured Value − Zero Code Error − Ideal Value
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD7225LPZ-REEL

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Digital to Analog Converters - DAC CMOS QUAD 8 BIT V-OUT IC
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