AD7225
Rev. C | Page 15 of 24
AGND BIAS
The AD7225 AGND pin can be biased above system ground
(AD7225 DGND) to provide an offset zero analog output
voltage level. Figure 18 shows a circuit configuration to achieve
this for DAC Channel A of the AD7225. The output voltage,
V
OUT
A, can be expressed as:
V
OUT
A = V
BIAS
+ D
A
(V
IN
)
where D
A
is a fractional representation of the digital word in
DAC Latch A (0 D
A
≤ 255/256).
V
DD
V
SS
AGND
V
BIAS
V
IN
DGND
V
OUT
A
DAC A
AD7225*
V
REF
A
*DIGITAL INPUTS OMITTED FOR CLARITY.
00986-018
Figure 18. AGND Bias Circuit
For a given V
IN
, increasing AGND above system ground reduces
the effective V
DD
V
REF
, which must be at least 4 V to ensure
specified operation. Note that, because the AGND pin is
common to all four DACs, this method biases up the output
voltages of all the DACs in the AD7225. Note that V
DD
and V
SS
of the AD7225 should be referenced to DGND.
AD7225
Rev. C | Page 16 of 24
AC REFERENCE SIGNAL
In some applications, it may be desirable to have ac reference
signals. The AD7225 has multiplying capability within the
upper (V
DD
4 V) and lower (2 V) limits of reference voltage
when operated with dual supplies. Therefore, ac signals need to
be ac-coupled and biased up before being applied to the
reference inputs. Figure 19 shows a sine wave signal applied to
V
REF
A. For input signal frequencies up to 50 kHz, the output
distortion typically remains less than 0.1%. The typical 3 dB
bandwidth figure for small signal inputs is 800 kHz.
*DIGITAL INPUTS OMITTED FOR CLARITY.
V
DD
V
SS
AGND DGND
V
OUT
A
DAC A
AD7225*
V
REF
A
+15V
+15V
15k
10k
+4V
–4V
REFERENCE
INPUT
00986-019
Figure 19. Applying an AC Signal to the AD7225
AD7225
Rev. C | Page 17 of 24
APPLICATIONS INFORMATION
h
1
1
T
X
n
h
2
2
T
X
n – 1
h
3
3
T
X
n – 2
h
4
4
X
n – 3
FILTER
INPUT
+
y(n)
FILTER
OUTPUT
AD7225
QUAD DAC
+
AD585
SHA
AD7225
QUAD DAC
AD7820
ADC
INPUT
SAMPLES
AM29520
TLC
DELAYED
INPUT
SAMPLES
AD584
REF
10V
V
REF
AM7224
DAC
V
OUT
V
REF
V
REF
A
V
OUT
A
h
1
V
REF
A
V
OUT
A
h
2
V
REF
A
V
OUT
A
h
3
V
REF
A
V
OUT
A
h
4
TAP WEIGHTGAIN SET
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
ACCUMULATOR
OUTPUT
FILTER
OUTPUT
00986-020
Figure 20. Programmable Transversal Filter
PROGRAMMABLE TRANSVERSAL FILTER
A discrete time filter can be described by either multiplication
in the frequency domain or by convolution in the time domain:
( ) ( ) ( )
=
+
=ωω=ω
N
k
knk
n
XhyorXHY
1
1
The convolution sum can be implemented using the special struc-
ture known as the transversal filter (see Figure 21). It consists
of an N-stage delay line with N taps weighted by N coefficients,
the resulting products being accumulated to form the output.
The tap weights or coefficients h
k
are the nonzero elements of
the impulse response and therefore determine the filter transfer
function. A particular filter frequency response is realized by
setting the coefficients to the appropriate values. This property
leads to the implementation of transversal filters whose fre-
quency response is programmable.
h
1
1
T
X
n
h
2
2
T
X
n – 1
h
3
3
X
n – 2
h
N
N
X
n – N + 1
h
N – 1
N –1
T
X
n – N
FILTER
INPUT
+
X
n – k + 1
h
k
y
n
=
N
k = 1
FILTER
OUTPUT
00986-021
Figure 21. Transversal Filter
A four-tap programmable transversal filter can be implemented
using the AD7225 (see Figure 20). The input signal is first sampled
and converted to allow the tapped delay line function to be
provided by the AM29520. The multiplication of delayed input
samples by fixed, programmable up weights is accomplished by
the AD7225, the four coefficients or reference inputs being set
by the digital codes stored in the AD7226. The resultant products
are accumulated to yield the convolution sum output sample,
which is held by the AD585.
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0 0.
05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
GAIN (dB)
NORMALIZED FREQUENCY (f/f
S
)
h
1
= 0.117
h
2
= 0.417
h
3
= 0.417
h
4
= 0.417
00986-022
Figure 22. Predicted (Theoretical) Response
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0 0.
05 0.10 0.
15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
GAIN (dB)
FREQUENCY (f/f
S
)
h
1
(DAC A) = 00011110
h
2
(DAC B) = 01101011
h
3
(DAC C) = 01101011
h
4
(DAC D) = 00011110
00986-023
Figure 23. Actual Response
Low-pass, band-pass, and high-pass filters can be synthesized
using this arrangement. The particular up weights needed for
any desired transfer function can be obtained using the standard
Remez exchange algorithm. Figure 22 shows the theoretical
low-pass frequency response produced by a four-tap transversal
filter with the coefficients indicated. Although the theoretical
prediction does not take into account the quantization of the
input samples and the truncation of the coefficients, neverthe-

AD7225LPZ-REEL

Mfr. #:
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Description:
Digital to Analog Converters - DAC CMOS QUAD 8 BIT V-OUT IC
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