©2011 Silicon Storage Technology, Inc. DS25076A 10/11
14
512 Kbit SPI Serial Flash
SST25VF512
Data Sheet
Microchip Technology Company
Block-Erase
The Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-
Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any com-
mand sequence. The Block-Erase instruction is initiated by executing an 8-bit command, 52H, followed
by address bits [A
23
-A
0
]. Address bits [A
MS
-A
15
](A
MS
= Most significant address) are used to deter-
mine block address (BA
X
), remaining address bits can be V
IL
or V
IH
. CE# must be driven high before the
instruction is executed. The user may poll the Busy bit in the software status register or wait T
BE
for the com-
pletion of the internal self-timed Block-Erase cycle. See Figure 8 for the Block-Erase sequence.
Figure 8: Block-Erase Sequence
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored
if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence.
The Chip-Erase instruction is initiated by executing an 8-bit command, 60H. CE# must be driven high
before the instruction is executed. The user may poll the Busy bit in the software status register or wait T
CE
for the completion of the internal self-timed Chip-Erase cycle. See Figure 9 for the Chip-Erase
sequence.
Figure 9: Chip-Erase Sequence
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.
52
HIGH IMPEDANCE
15 16
23
24
31
MODE 0
MODE 3
1192 F28.11
MSB MSB
CE#
SO
SI
SCK
01234567
60
HIGH IMPEDANCE
MODE 0
MODE 3
1192 F07.12
MSB
