©2011 Silicon Storage Technology, Inc. DS25076A 10/11
9
512 Kbit SPI Serial Flash
SST25VF512
Data Sheet
Microchip Technology Company
Instructions
Instructions are used to Read, Write (Erase and Program), and configure the SST25VF512. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut-
ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or
Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list
of the instructions is provided in Table 5. All instructions are synchronized off a high to low transition of
CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must
be driven low before an instruction is entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read-ID and Read-Status-Register instructions). Any low to high
transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction
in progress and return the device to the standby mode. Instruction commands (Op Code), addresses,
and data are all input from the most significant bit (MSB) first.
Table 5: Device Operation Instructions
1
1. A
MS
= Most Significant Address
A
MS
=A
15
for SST25VF512
Address bits above the most significant bit of each density can be V
IL
or V
IH
Bus Cycle
2
2. One bus cycle is eight clock periods.
123 45
Cycle Type/Operation
3,4
3. Operation: S
IN
= Serial In, S
OUT
= Serial Out
4. X = Dummy Input Cycles (V
IL
or V
IH
); - = Non-Applicable Cycles (Cycles are not necessary)
S
IN
S
OUT
S
IN
S
OUT
S
IN
S
OUT
S
IN
S
OUT
S
IN
S
OUT
Read 03H Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z X D
OUT
Sector-Erase
5,6
5. Sector addresses: use A
MS
-A
12
, remaining addresses can be V
IL
or V
IH
6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable
(WREN) instruction must be executed.
20H Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z - -
Block-Erase
5,7
7. Block addresses for: use A
MS
-A
15
, remaining addresses can be V
IL
or V
IH
52H Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z - -
Chip-Erase
6
60H Hi-Z - - - - - - - -
Byte-Program
6
02H Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z D
IN
Hi-Z
Auto Address Increment
(AAI) Program
6,8
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
followed by the data to be programmed.
AFH Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z D
IN
Hi-Z
Read-Status-Register
(RDSR)
05H Hi-Z X D
OUT
- Note
9
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
- Note
9
- Note
9
Enable-Write-Status-Reg-
ister (EWSR)
10
10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in
conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR
instruction to make both instructions effective.
50H Hi-Z - - - - - - - -
Write-Status-Register
(WRSR)
10
01H Hi-Z Data Hi-Z - - -. - - -
Write-Enable (WREN) 06H Hi-Z - - - - - - - -
Write-Disable (WRDI) 04H Hi-Z - - - - - - - -
Read-ID 90H or
ABH
Hi-Z 00H Hi-Z 00H Hi-Z ID
Addr
11
Hi-Z X D
OUT
12
T5.18 25076
