932SQ420DKLFT Datasheet 932SQ420DGLFT, 932SQ420DKLF, 932SQ420DGLF | P1-P3

DATASHEET

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS

932SQ420D

IDT®

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 1

932SQ420D REV J 010715

General Description

The 932SQ420D is a main clock synthesizer for

Romley-generation Intel based server platforms. The

932SQ420D is driven with a 25 MHz crystal for maximum

performance. It generates CPU outputs of 100 or 133.33

MHz.

Recommended Application

CK420BQ

Output Features

• 4 - HCSL CPU outputs

• 4 - HCSL Non-Spread SAS/SRC outputs

• 3 - HCSL SRC outputs

• 1 - HCSL DOT96 output

• 1 - 3.3V 48M output

• 5 - 3.3V PCI outputs

• 1- 3.3V REF output

Features/Benefits

• 0.5% down spread capable on CPU/SRC/PCI

outputs/Lower EMI

• 64-pin TSSOP and MLF packages/Space Savings

Key Specifications

• Cycle to cycle jitter: CPU/SRC/NS_SRC/NS_SAS <

50ps.

• Phase jitter: PCIe Gen2 < 3ps rms, Gen3 < 1ps rms

• Phase jitter: QPI 9.6GB/s < 0.2ps rms

• Phase jitter: NS-SAS < 0.4ps rms using raw phase data

• Phase jitter: NS-SAS < 1.3ps rms using Clk Jit Tool 1.6.3

Block Diagram

Logic

X1_25

SRC(2:0)

SMBDAT

SMBCLK

CKPWRGD#/PD

IREF

100M_133M#

CPU_SRC_PCI

PLL (SS)

CPU(3:0)

Low Drift non-SS

PLL

<500ps LTJ

NS_SAS(1:0)

(

)

DOT96

48M

PCI(4:0)

14.31818MHz

Non-SS PLL

REF14M

Test_Mode

Test_Sel

Non-SS PLL

932SQ420D

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS

IDT®

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 2

932SQ420D REV J 010715

Pin Configuration - 64TSSOP

Spread Spectrum Control

Power Group Pin Numbers

932SQ420 Power Down Functionality

SMBCLK 1 64 SMBDAT

GND14 2 63 VDDCPU

AVDD14 3 62 CPU3 T

VDD14 4 61 CPU3C

REF14_3x/TEST_SEL 5 60 CPU2T

GND14 6 59 CPU2C

GNDXTAL 7 58 GNDCPU

X1_25 8 57 VDDCPU

X2_25 9 56 CPU1T

VDDXTAL10 55CPU1C

GNDPCI 11 54 CPU0T

VDDPCI 12 53 CPU0C

PCI4_2x 13 52 GNDNS

PCI3_2x 14 51 AVDD_NS_SAS

PCI2_2x 15 50 NS_SAS1T

PCI1_2x 16 49 NS_SAS1C

PCI0_2x 17 48 NS_SAS0T

GNDPCI 18 47 NS_SAS0C

VDDPCI 19 46 GNDNS

VDD4820 45VDDNS

48M_2x/100M_133M# 21 44 NS_SRC1T

GND4822 43NS_SRC1C

GND9623 42NS_SRC0T

DOT96T 24 41 NS_SRC0C

DOT96C 25 40 IREF

AVDD96 26 39 GNDSRC

TEST_MODE 27 38 AVDD_SRC

CKPWRGD#/PD 28 37 VDDSRC

VDDSRC 29 36 SRC2T

SRC0T 30 35 SRC2C

SRC0C 31 34 SRC1T

GNDSRC 32 33 SRC1C

64-TSSOP

Note: Pins with ^ prefix have internal 120K pullup

Pins with v prefix have internal 120K pulldown

932SQ420

SS_Enable

(B1b0)

CPU, SRC &

PCI

0OFF

1ON

VDD GND VDD GND

57 56 3 2 14MHz PLL Analog

58 60 4 6 REF14M Output and Logic

64 61 10 7 25MHz XTAL

2, 9 1, 8 12, 19 11, 18 PCI Outputs and Logic

10 12 20 22 48MH z Output and Logic

16 13 26 23 96MH z PLL Analog, Output and Logic

19, 27 22 29, 37 32 SRC Out puts and Logic

28 29 38 39 SRC PLL Analog

35 36 45 46

Non-Spreading Differential Outputs & Logic

41 42 51 52 NS-SAS/SRC PLL Analog

47, 53 48 57,63 58 CPU Outputs and Logic

MLF

Description

TS SOP

CKPWRGD#/PD

Differential

Outputs

Single-ended

Outputs

Single ended

Outputs w/Latch

1HI-Z

Low

2. These outputs are Hi-Z after VDD is applied and before the first

assertion of CKPWRGD #.

Running

1. Hi-Z on the differential outputs will result in both True and

Complement being low due to the termination network

932SQ420D

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS

IDT®

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 3

932SQ420D REV J 010715

Pin Descriptions - 64 TSSOP

PIN # PIN NAME TYPE DESCRIPTION

1 SMBCLK IN Clock pin of SMBUS circuitry, 5V toleran t

2 GND14 PWR Ground pin for 14MHz output and logic.

3 AVDD14 PWR Analog power pin for 14MHz PLL

4 VDD14 PWR Power pin for 14MHz output and logic

5 vREF14_3x/TEST_SEL I/O

14.318 MHz reference clock. 3X drive strength as default / TEST_SEL latched input to enable test mode.

Refer to Test Clarification Table. This pin has a weak (~120Kohm) internal pull down.

6 GND14 PWR Ground pin for 14MHz output and logic.

7 GNDXTAL PWR Ground pin for Crystal Oscillator.

8 X1_25 IN Crystal input, Nominally 25.00MHz.

9 X2_25 OUT Crystal output, Nominally 25.00MHz.

10 VDDXTAL PWR 3.3V power for the crystal oscillator.

11 GNDPCI PWR Ground pin for PCI outputs and logic.

12 VDDPCI PWR 3.3V power for the PCI outputs and logic

13 PCI4_2x OUT 3.3V PCI clock output

14 PCI3_2x OUT 3.3V PCI clock output

15 PCI2_2x OUT 3.3V PCI clock output

16 PCI1_2x OUT 3.3V PCI clock output

17 PCI0_2x OUT 3.3V PCI clock output

18 GNDPCI PWR Ground pin for PCI outputs and logic.

19 VDDPCI PWR 3.3V

ower for the PCI out

uts and lo

20 VDD48 PWR 3.3V

ower for the 48MHz out

ut and lo

21 ^48M_2x/100M_133M# I/O

3.3V 48MHz output/ 3.3V tolerant CPU frequency select latched input pin. See VilFS and VihFS values for

thresholds. This pin ha s a weak (~120Kom) internal pull up.

1 = 100MHz, 0 = 133MHz o

eratin

fre

uenc

22 GND48 PWR Ground

in for 48MHz out

ut and lo

ic.

23 GND96 PWR Ground

in for DOT96 out

ut and lo

ic.

24 DOT96T OUT

True clock of differential 96MHz output. These are current mode outputs. These are current mode outputs

and external 33 ohm series resistors and 49.9 ohm shunt resistors are re

uired for termination.

25 DOT96C OUT

Complementary clock of differential 96MHz output. These are current mode outputs and external 33 ohm

series resistors and 4 9.9 ohm shunt resistors are re

uired for termination.

26 AVDD96 PWR 3.3V

ower for the 48/96MHz PLL and the 96MHz out

ut and lo

27 TEST_ MODE IN

TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to

Test Clarification Table.

28 CKPWRGD#/PD IN

CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power Up. PD is an

asynchronous active high input pin used to put the device into a low power state. The internal clocks and PLLs

are sto

ed.

29 VDDSRC PWR 3.3V power for the SRC outputs and logic

30 SRC0T OUT

True clock of differential SRC outp ut. These are current mode outputs. These are current mode outputs and

external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.

31 SRC0C OUT

Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm

series resistors and 4 9.9 ohm shunt resistors are re

uired for termination.

32 GNDSRC PWR Ground pin for SRC outputs and logic.

33 SRC1C OUT

Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm

series resistors and 4 9.9 ohm shunt resistors are required for termination.

34 SRC1T OUT

True clock of differential SRC outp ut. These are current mode outputs. These are current mode outputs and

external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.

35 SRC2C OUT

Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm

series resistors and 4 9.9 ohm shunt resistors are required for termination.

36 SRC2T OUT

True clock of differential SRC outp ut. These are current mode outputs. These are current mode outputs and

external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.

37 VDDSRC PWR 3.3V power for the SRC outputs and logic

38 AVDD_SRC PWR 3.3V power for the SRC PLL analog circuits

39 GNDSRC PWR Ground pin for SRC outputs and logic.

40 IREF OUT

This pin establishes the referen ce current for the differential current-mode output pairs. This pin requires a

fixed precision resistor tied to ground in order to establish the appro priate current. 475 ohms is the standard

va lue .

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

932SQ420DKLFT

Mfr. #:

Buy 932SQ420DKLFT

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner CK420BQ

Lifecycle:

New from this manufacturer.

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932SQ420DKLFT

932SQ420DKLFT

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