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932SQ420DKLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
932SQ420D
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
IDT®
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 10
932SQ420D REV J 010715
Electrical Characteristics - Input/Supply/Common Parameters
TA = T
COM;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Ambient Operating
Tem
p
erature
T
COM
Commmercial range 0 70 °C 1
Input High Voltage
V
IH
Single-ended inputs, except
SMBus, low threshold and tri-
level in
p
uts
2
V
DD
+ 0.3
V1
Input Low Voltage
V
IL
Single-ended inputs, except
SMBus, low threshold and tri-
level in
p
uts
GND
- 0.3
0.8 V 1
I
IN
Single-ended inputs,
V
IN
= GND, V
IN
= V DD
-5 5 uA 1
I
INP
Single-ended inputs.
V
IN
= 0 V; Inputs with internal pull
-
up resistors
V
IN
= VDD; Inputs with internal
pull-dow n resistors
-200 200 uA 1
Low Threshold Input-
Hi
g
h Volta
g
e
V
IH _FS
3.3 V +/-5% 0.7 V
DD
+ 0.3 V 1
Low Threshold Input-
Low Volta
g
e
V
IL_FS
3.3 V +/-5%
V
SS
- 0.3
0.35 V 1
Input Frequency
F
i
25.00 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs 5 pF 1
C
OUT
Output pin capacitance 5 pF 1
C
INX
X1 & X2 pins 5 pF 1
Clk Stabilization
T
STAB
From V
DD
Power-Up and after
input clock stabilization or de-
assertion of PD# to 1st clock
1.8 ms 1,2
SS Modulation Frequency
f
MODIN
Allowable Frequency
(
Trian
g
ular Modulation
)
30 31.50 0 33 kHz 1
Tdrive_PD#
t
DR VPD
Differential output enable after
PD# de-assertion
200.000 300 us 1,3
Tfall t
F
Fall time of control inputs 5 ns 1,2
Trise
t
R
Rise time of control inputs 5 ns 1,2
SMBus Inp ut Low Voltage
V
ILSMB
0.8 V 1
SMBus Input
Hi
g
h Volta
g
e
V
IH SMB
2.1
V
DDSMB
V1
SMBus Output
Low Volta
g
e
V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PU LLU P
@ V
OL
4mA1
Nominal Bus Voltage
V
DDSM B
3V to 5V +/- 10% 2.7 5.5 V 1
SCLK/SDATA Rise Time
t
RSMB
(Max VIL - 0.15) to (Min VIH +
0.15
)
1000 ns 1
SCLK/SDATA Fall Time
t
FSMB
(Min VIH + 0.15) to (Max VIL -
0.15
)
300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating
frequency
100 kHz 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are >200 mV
Input Current
Capacitance
932SQ420D
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
IDT®
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 11
932SQ420D REV J 010715
AC Electrical Characteristics - Differential Current Mode Outputs
Electrical Characteristics - Phase Jitter Parameters
TA = T
COM;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Duty Cycle t
DC
Measured differentially, PLL
Mode
45 50.1 55 % 1
Skew, Output to Output
t
sk3 SRC
Across all SRC outputs,
V
T
= 50%
13.5 50 ps 1
Skew, Output to Output
t
sk3 CPU
Across all CPU outputs,
V
T
= 50%
43 50 ps 1
CPU, SRC, NS_SAS out
p
uts 35 50
p
s1,3
DOT96 out
p
ut 75 250
p
s1,3
1
Guaranteed by design and characterization, not 100% tested in production.
2
I
REF
= V
DD
/(3xR
R
). For R
R
= 475
Ω
(1 %), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
.
3
Measured from differential waveform
t
jcyc-cyc
Jitter, Cycle to cycle
T
A
= 0 - 70°C; Supply Voltage V
DD/
V
DDA
= 3.3 V +/-5%,
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
t
jp
hPCIeG1
PCIe Gen 1 28 86 ps (p-p) 1,2,3,6
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.9 3
ps
(rms)
1,2,6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
1.7
3.1
ps
(rms)
1,2,6
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR =
10MHz)
0.4
1
ps
(rms)
1,2,4,6
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s,
6.4Gb/s 12UI)
0.15 0.5
ps
(rms)
1,5,7
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
0.13 0.3
ps
(rms)
1,5,7
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
0.11 0.2
ps
(rms)
1,5,7
t
jphSAS12G
SAS12G
(Filtered REFCLK Jitter 20KHz
to 20MHz.)
0.34 0.4
ps
(rms)
1,8,9
t
jphSAS12G
SAS 12G 0.70 1.3
ps
(rms)
1,5,8
1
Guaranteed by design and characterization, not 100% tested in production.
6
Applied to SRC outputs
7
Applies to CPU outputs
8
Applies to NS_SAS, NS_SRC outputs, Spread Off
9
Intel calculation from raw phase noise data
Phase Jitter
t
jphPCIeG2
t
jphQPI_SMI
2
See http://www.pcisig.com for complete specs
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
Subject to final radification by PCI SIG.
5
Calculated from Intel-supplied Clock Jitter Tool v 1.6.6
932SQ420D
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
IDT®
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 12
932SQ420D REV J 010715
Electrical Characteristics - PCI
Electrical Characteristics - 48MHz
Electrical Characteristics - Current Consumption
T
A
= 0 - 70°C; Supply Voltage V
DD /
V
DD A
= 3.3 V +/-5% ,
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Output Impedance R
DSP
V
O
= V
DD
*(0.5) 12 55
Ω
1
Output High Voltage V
OH
I
OH
= -1 mA 2.4 V 1
Output Low Voltage V
OL
I
OL
= 1 mA 0.55 V
1
MIN @V
OH
= 1.0 V -3 3 mA 1
MAX @V
OH
= 3.135 V
-33 mA 1
MIN @V
OL
= 1.95 V
30 mA 1
MAX @ V
OL
= 0.4 V 38 mA 1
Clock High Time T
HIGH
1.5V 12
ns
1
Clock Low Time T
LOW
1.5V 12 ns
1
Edge Rate
t
sle wr/ f
Rising/Falling edge rate 1 1.8 4 V/ns 1,2
Duty Cycle
d
t1
V
T
= 1.5 V 45 50.5 55
%1
Group Skew t
skew
V
T
= 1.5 V 294 500 ps 1
Jitter, Cycle to cycle
t
jcyc-cyc
V
T
= 1.5 V
108 500 ps
1
See "Single-ended Test Loads Page" for termination circuits
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured between 0.8V and 2.0V
Output High C urrent
I
OH
Output Low Current
I
OL
T
A
= 0 - 70°C; Supply Voltage V
DD /
V
DD A
= 3.3 V +/-5% ,
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Output Impedance R
DSP
V
O
= V
DD
*(0.5) 20 60
Ω
1
Output High Voltage V
OH
I
OH
= -1 mA 2.4 V 1
Output Low Voltage V
OL
I
OL
= 1 mA 0.55 V
1
MIN @V
OH
= 1.0 V -29 m A 1
MAX @V
OH
= 3.135 V
-33 mA 1
MIN @V
OL
= 1.9 5 V
29 mA 1
MAX @ V
OL
= 0.4 V 27 mA 1
Clock High Time T
HIGH
1.5V 8.094 10.036
ns
1
Clock Low Time T
LOW
1.5V 7.694 9.836 ns
1
Edge R ate
t
slewr/f_USB
Rising/Falling edge rate 1 1.5 2 V/ns 1,2
Duty Cycle d
t1
V
T
= 1.5 V 455155%1
Jitter, Cycle to cycle
t
jcyc-cyc
V
T
= 1.5 V
109 350 ps
1
See "Single-ended Test Loads Page" for termination circuits
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured between 0.8V and 2.0V
Output High Current
I
OH
Output Low Current
I
OL
TA = T
COM;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Operating Supply Current
I
DD3.3OP
All outputs active @100MHz, C
L
= Full lo ad;
380 400 mA 1
Powerdown Current
I
DD3.3PDZ
All differential pairs tri-stated 16 20 mA
1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
ro duc tio n.
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932SQ420DKLFT

Mfr. #:
Buy 932SQ420DKLFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner CK420BQ
Lifecycle:
New from this manufacturer.
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