COMMERCIAL TEMPERATURE RANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
18
Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values (IDT Standard and FWFT Modes)
Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(IDT Standard and FWFT Modes)
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one CLKB cycle later than shown.
2. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FFA/IRA and FFB/IRB is set HIGH.
3. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2).
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one CLKB cycle later than shown.
2. CSA=LOW, W/RA=HIGH,MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
4677 drw07
CLKA
MRS1,
MRS2
FFA/IRA
CLKB
FFB/IRB
A0-A35
FS1,FS0
ENA
t
FSH
t
WFF
t
ENH
t
ENS2
t
SKEW1
t
DS
t
DH
t
WFF
4
0,0
AFA Offset
(Y1)
AEB Offset
(X1)
AFB Offset
(Y 2)
AEA Offset
(X 2)
First Word to FIFO1
12
(1)
t
FSH
t
FSS
t
FSS
1
2
FS2
CLKA
FFA/IRA
t
SENS
t
SENH
FS0/SD
(3)
t
SPH
t
SENS
t
SENH
t
FSS
t
WFF
FS1/SEN
AEA Offset (X2) LSB
t
SDS
t
SDH
t
SDS
t
SDH
AFA Offset (Y1) MSB
MRS1,
MRS2
4
4677 drw08
t
FSS
t
FSH
CLKB 4
FS2
FFB/IRB
t
WFF
t
SKEW
(1)
