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IDT72V36104L10PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
COMMERCIAL TEMPERATURE RANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
34
CLKA
ENB
CLKB
RT1
4664 drw 33
t
RSTS
t
RSTH
t
REF
(2)
B0-Bn
RTM
ORB
t
REF
(2)
W1
Wx
t
A
13
4
2
1
342
t
RTMS
t
RTMH
LOW
NOTES:
1. CSB = LOW
2. Retransmit setup is complete after ORB returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, IRA will be LOW throughout the Retransmit
setup procedure. D = 16,385, 32,769 and 65,537 for the IDT72V3684, IDT72V3694 and IDT72V36104 respectively.
Figure 31. Retransmit Timing for FIFO1 (FWFT Mode)
CLKB
ENA
CLKA
RT2
4677 drw34
tRSTS
tRSTH
tREF
(2)
A0-An
RTM
ORA
tREF
(2)
W1
Wx
tA
13
4
2
1
342
t
RTMS
tRTMH
LOW
NOTES:
1. CSA = LOW
2. Retransmit setup is complete after ORA returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO2 after Master Reset on FIFO2.
4. No more than D-2 may be written to the FIFO2 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, IRB will be LOW throughout the Retransmit
setup procedure. D = 16,385, 32,769 and 65,537 for the IDT72V3684, IDT72V3694 and IDT72V36104 respectively.
Figure 32. Retransmit Timing for FIFO2 (FWFT Mode)
COMMERCIAL TEMPERATURE RANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
35
Figure 33. Output Load and AC Test Conditions
NOTE:
1. Includes probe and jig capacitance.
4677 drw35
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
330
Ω
3.3V
510
Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
GND
Timing
Input
Data,
Enable
Input
GND
3 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3 V
GND
GND
3 V
1.5 V
1.5 V
1.5 V
1.5 V
t
W
Output
Enable
Low-Level
Output
High-Level
Output
3 V
OL
GND
≈3 V
1.5 V
1.5 V
1.5 V
1.5 V
OH
≈O V
GND
OH
OL
1.5 V
1.5 V
1.5 V
1.5 V
Input
In-Phase
Output
High-Level
Input
Low-Level
Input
V
V
V
V
1.5 V
3 V
t
S
t
h
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PD
t
PD
(1)
36
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753
San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com
www.idt.com
ORDERING INFORMATION
BLANK
G
PF
10
15
L
72V3684
72V3694
72V36104
4677 drw36
Commercial (0
o
C to +70
o
C)
Green
Thin Quad Flat Pack (TQFP, PK128-1)
Low Power
16,384 x 36 x 2 ⎯ 3.3V SyncBiFIFO with Bus-Matching
32,768 x 36 x 2 ⎯ 3.3V SyncBiFIFO with Bus-Matching
65,536 x 36 x 2 ⎯ 3.3V SyncBiFIFO with Bus-Matching
XXXXXX
Device Type
XXX X
Power Speed Package
X
Clock Cycle Time (t
CLK
)
Speed in Nanoseconds
Commercial Only
Process/
Temperature
Range
X
NOTES:
1. Industrial temperature range is available by special order.
2. Green parts available. For specific speeds and packages contact your sales office.
DATASHEET DOCUMENT HISTORY
10/31/2000 pgs. 1, 6, 8, 9, 12 and 36
12/14/2000 pgs. 4 and 5.
02/08/2001 pgs. 5 and 11.
03/27/2001 pgs. 6 and 7.
11/04/2003 pg. 1.
05/27/2008 pg. 1, 6, and 36.
02/05/2009 pg. 36.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36

IDT72V36104L10PF

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Description:
IC FIFO 131KX36 10NS 128QFP
Lifecycle:
New from this manufacturer.
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