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IDT72V36104L10PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
COMMERCIAL TEMPERATURE RANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
7
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3684/72V3694/72V36104 with CLKA
and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected
to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's inputs driven by TTL
HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
P
T = VCC x ICC(f) + Σ(CL x VCC
2
x fo)
N
where:
N = number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)
CL = output capacitance load
fo = switching frequency of an output
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
010203040506070
0
10
20
30
40
50
60
f
S
⎯
Clock Frequency
⎯
MHz
I
CC(f)
Supply Current
mA
f
data
= 1/2
f
S
T
A
= 25°C
C
L
= 0 pF
4677 drw03
70
90
80
100
80
90
100
V
CC =
3.3V
V
CC =
3.6V
V
CC =
3.0V
COMMERCIAL TEMPERATURE RANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
8
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
IDT72V3684L10 IDT72V3684L15
IDT72V3694L10 IDT72V3694L15
IDT72V36104L10 IDT72V36104L15
Symbol Parameter Min. Max. Min. Max. Unit
fS Clock Frequency, CLKA or CLKB — 100 — 66.7 MHz
tCLK Clock Cycle Time, CLKA or CLKB 10 — 15 — ns
t
CLKH Pulse Duration, CLKA or CLKB HIGH 4.5 — 6 — ns
t
CLKL Pulse Duration, CLKA and CLKB LOW 4.5 — 6 — ns
tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑ 3—4 —ns
t
ENS1 Setup Time, CSA and W/RA before CLKA↑; CSB and 4 — 4.5 — ns
W/RB before CLKB↑
tENS2 Setup Time, ENA, and MBA before CLKA↑; ENB, and 3 — 4.5 — ns
MBB before CLKB↑
tRSTS Setup Time, MRS1, MRS2, PRS1, or PRS2 LOW before 5 — 5 — ns
CLKA↑ or CLKB↑
(1)
tFSS Setup Time, FS0, FS1, FS2 before MRS1 and MRS2 HIGH 7.5 — 7.5 — ns
tBES Setup Time, BE/FWFT before MRS1 and MRS2 HIGH 7.5 — 7.5 — ns
tSDS Setup Time, FS0/SD before CLKA↑ 3—4 —ns
tSENS Setup Time, FS1/SEN before CLKA↑ 3—4 —ns
tFWS Setup Time, BE/FWFT before CLKA↑ 0—0 —ns
tRTMS Setup Time, RTM before RT1; RTM before RT2 5—5 —ns
tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑ 0.5 — 1 — ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, 0.5 — 1 — ns
W/RB, ENB, and MBB after CLKB↑
tRSTH Hold Time, MRS1, MRS2, PRS1 or PRS2 LOW after CLKA↑ 4—4 —ns
or CLKB↑
(1)
tFSH Hold Time, FS0, FS1, FS2 after MRS1 and MRS2 HIGH 2 — 2 — ns
tBEH Hold Time, BE/FWFT after MRS1 and MRS2 HIGH 2 — 2 — ns
tSDH Hold Time, FS0/SD after CLKA↑ 0.5 — 1 — ns
tSENH Hold Time, FS1/SEN HIGH after CLKA↑ 0.5 — 1 — ns
tSPH Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH 2 — 2 — ns
tRTMH Hold Time, RTM after RT1; RTM after RT2 5—5 —ns
tSKEW1
(2)
Skew Time between CLKA↑ and CLKB↑ for EFA/ORA, 5 — 7.5 — ns
EFB/ORB, FFA/IRA, and FFB/IRB
tSKEW2
(2.3)
Skew Time between CLKA↑ and CLKB↑ for AEA, AEB, AFA,12 —12 —ns
and AFB
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
(Vcc = 3.3V ± 0.15V; TA = 0
ο
C to +70
ο
C; JEDEC JESD8-A compliant)
COMMERCIAL TEMPERATURE RANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
9
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C
L = 30pF
IDT72V3684L10 IDT72V3684L15
IDT72V3694L10 IDT72V3694L15
IDT72V36104L10 IDT72V36104L15
Symbol Parameter Min. Max. Min. Max. Unit
tA Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 2 6.5 2 10 ns
tWFF Propagation Delay Time, CLKA↑ to FFA/IRA and CLKB↑ 2 6.5 2 8 ns
to FFB/IRB
tREF Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ 1 6.5 1 8 ns
to EFB/ORB
tPAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to 1 6.5 1 8 ns
AEB
tPAF Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to 1 6.5 1 8 ns
AFB
tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 0 6.5 0 8 ns
HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH
tPMR Propagation Delay Time, CLKA↑ to B0-B35
(1)
and CLKB↑ 38 210ns
to A0-A35
(2)
tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to 3 6.5 2 10 ns
B0-B35 valid
tRSF Propagation Delay Time, MRS1 or PRS1 LOW to AEB 110 115ns
LOW, AFA HIGH, and MBF1 HIGH and MRS2 or PRS2
LOW to AEA LOW, AFB HIGH, and MBF2 HIGH
tEN Enable Time, CSA or W/RA LOW to A0-A35 Active and 2 6 2 10 ns
CSB LOW and W/RB HIGH to B0-B35 Active
tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high- 1 6 1 8 ns
impedance and CSB HIGH or W/RB LOW to B0-B35 at
high-impedance
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
(Vcc = 3.3V ± 0.15V; TA = 0
ο
C to +70
ο
C; JEDEC JESD8-A compliant)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36

IDT72V36104L10PF

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IC FIFO 131KX36 10NS 128QFP
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