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IDT72V36104L10PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
COMMERCIAL TEMPERATURE RANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
4
PIN DESCRIPTIONS
Symbol Name I/O Description
A0-A35 Port A Data I/O 36-bit bidirectional data port for side A.
AEA Port A Almost- O Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in
Empty Flag FIFO2 is less than or equal to the value in the Almost-Empty A Offset register, X2.
AEB Port B Almost- O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in
Empty Flag FIFO1 is less than or equal to the value in the Almost-Empty B Offset register, X1.
AFA Port A Almost- O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations
Full Flag in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
AFB Port B Almost- O Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty
Full Flag locations in FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.
B0-B35 Port A Data I/O 36-bit bidirectional data port for side B.
BE/FWFT Big-Endian/ I This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. In
First Word this case, depending on the bus size, the most significant byte or word on Port A is read from Port B
Fall Through first (A-to-B data flow) or written to Port B first (B-to-A data flow). A LOW on BE will select Little-Endian
Select operation. In this case, the least significant byte or word on Port A is read from Port B first (for A-to-B data
flow) or written to Port B first (B-to-A data
flow). After Master Reset, this pin selects the timing mode. A
HIGH on FWFT
selects IDT Standard mode, a LOW selects First Word Fall Through mode. Once the
timing mode has been selected, the level on FWFT must be static throughout device operation.
BM
(1)
Bus-Match Select I
A HIGH on this pin enables either byte or word bus width on Port B, depending
on the state of SIZE.
(Port B) A LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian
arrangement for Port B. The level of BM must be static throughout device operation.
CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through Port A and can be
asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the
LOW-to-HIGH transition of CLKA.
CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through Port B and can be
asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are synchronized to the
LOW-to-HIGH transition of CLKB.
CSA Port A Chip Select I CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35
outputs are in the high-impedance state when CSA is HIGH.
CSB Port B Chip Select I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B. The
B0-B35 outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA Port A Empty/ O This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA
Output Ready Flag indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is
selected. ORA indicates the presence of valid data on A0-A35 outputs, available for reading. EFA/ORA
is synchronized to the LOW-to-HIGH transition of CLKA.
EFB/ORB Port B Empty/ O This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates
Output Ready Flag whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB
indicates the presence of valid data on the B0-B35 outputs, available for reading. EFB/ORB is
synchronized to the LOW-to-HIGH transition of CLKB.
ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
FFA/IRA Port A Full/ O This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates
Input Ready Flag whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA
indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is
synchronized to the LOW-to-HIGH transition of CLKA.
FFB/IRB Port B Full/ O This is a dual function pin. In the IDT Standard mode, the FFB function is selected. FFB indicates
Input Ready Flag whether or not the FIFO2 memory is full. In the
FWFT mode, the IRB function is selected. IRB
indicates whether or not there is space available for writing to the FIFO2 memory. FFB/IRB is
synchronized to the LOW-to-HIGH transition of CLKB.
COMMERCIAL TEMPERATURE RANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
5
Symbol Name I/O Description
FS0/SD Flag Offset Select 0/ I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master
Serial Data Reset, FS1/SEN and FS0/SD, together with FS2, select the flag offset programming method. Three offset
register programming methods are available: automatically load one of five preset values (8, 16, 64, 256 or
1,024), parallel load from Port A, and serial load.
FS1/SEN Flag Offset Select 1/ I
Serial Enable, When serial load is selected for flag offset register programming, FS1/SEN is used as an enable
synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load
FS2
(1)
Flag Offset Select 2 I the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program the offset
registers is 56 for the IDT72V3684, 60 for the IDT72V3694, and 64 for the IDT72V36104. The first bit write
stores the Y- register (Y1) MSB and the last bit write stores the X-register (X2) LSB.
MBA Port A Mailbox I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
Select outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level
selects FIFO2 output register data for output.
MBB Port B Mailbox I A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35
Select outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level
selects FIFO1 output register data for output.
MBF1 Mail1 Register O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1
Flag register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a
Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2 Mail2 Register O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2
Flag register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port
A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MRS1 FIFO1 Master I A LOW on this pin initializes the FIFO1 read and write pointers to the first location
of memory and sets the Port
Reset
B output register to all zeroes. A LOW-to-HIGH transition
on MRS1 selects the programming method (serial or parallel)
and one of five programmable flag default offsets for FIFO1 and FIFO2. It also configures Port B for bus size and
endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while MRS1 is LOW.
MRS2 FIFO2 Master I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
Reset output register to all zeroes. A LOW-to-HIGH transition on MRS2, toggled simultaneously with MRS1, selects the
programming method (serial or parallel) and one of the programmable flag default offsets for
FIFO2. Four LOW-to-
HIGH transitions of CLKA and four LOW-to-HIGH transitions
of CLKB must occur while MRS2 is LOW.
PRS1/ Partial Reset/ I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin.
RT1 Retransmit FIFO1 If RTM is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO1 and initializes the FIFO1 read
and write pointers to the first location of memory and sets the Port B output register to all zeroes. During Partial Reset,
the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable
flag settings are all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO1 read
pointer only to the first memory location.
PRS2/ Partial Reset/ I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin.
RT2 Retransmit FIFO2 If RTM is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO2 and initializes the FIFO2 read
and write selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag
settings are all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO2 read pointer
only to the first memory location.
RTM Retransmit Mode I This pin is used in conjunction with the RT1 and RT2 pins. When RTM is HIGH a Retransmit is performed on
FIFO1 or FIFO2 respectively.
SIZE
(1)
Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH
selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port
B. The level of SIZE must be static throughout device operation
W/RA Port-A Write/ I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH
Read Select transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
W/RB Port-B Write/ I A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH
Read Select transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.
PIN DESCRIPTIONS (CONTINUED)
NOTE:
1. FS2, BM and SIZE inputs are not TTL compatible. These inputs should be tied to GND or VCC.
COMMERCIAL TEMPERATURE RANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
6
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-
AIR TEMPERATURE RANGE (Unless otherwise noted)
Symbol Rating Commercial Unit
VCC Supply Voltage Range –0.5 to +4.6 V
VI
(2)
Input Voltage Range –0.5 to VCC+0.5 V
VO
(2)
Output Voltage Range –0.5 to VCC+0.5 V
IIK Input Clamp Current (VI < 0 or VI > VCC) ±20 mA
IOK Output Clamp Current (VO = < 0 or VO > VCC) ±50 mA
I
OUT Continuous Output Current (VO = 0 to VCC) ±50 mA
I
CC Continuous Current Through VCC or GND ±400 mA
TSTG Storage Temperature Range –65 to 150 °C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)
(1)
NOTES:
1. All typical values are at VCC = 3.3V, TA = 25°C.
2. Vcc = 3.3V ± 0.15V, TA = 0° to +70°; JEDEC JESD8-A compliant
3. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
4. Characterized values, not currently tested.
RECOMMENDED OPERATING CONDITIONS
NOTE:
1. Vcc = 3.3V ± 0.15V, JEDEC JESD8-A compliant
Symbol Parameter Min. Typ. Max. Unit
VCC
(1)
Supply Voltage 3.15 3.3 3.45 V
V
IH High-Level Input Voltage 2 — VCC+0.5 V
V
IL Low-Level Input Voltage — — 0.8 V
IOH High-Level Output Current — — –4 mA
I
OL Low-Level Output Current — — 8 mA
T
A Operating Temperature 0 — 70 °C
IDT72V3684
IDT72V3694
IDT72V36104
Commercial
tCLK = 10, 15 ns
(2)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VOH Output Logic "1" Voltage VCC = 3.0V, IOH = –4 mA 2.4 — — V
VOL Output Logic "0" Voltage VCC = 3.0V, IOL = 8 mA — — 0.5 V
ILI Input Leakage Current (Any Input) VCC = 3.6V, VI = VCC or 0 — — ±5 µA
I
LO Output Leakage Current VCC = 3.6V, VO = VCC or 0 — — ±5 µA
ICC2
(3)
Standby Current (with CLKA and CLKB running) VCC = 3.6V, VI = VCC - 0.2V or 0 — — 15 mA
ICC3
(3)
Standby Current (no clocks running) VCC = 3.6V, VI = VCC - 0.2V or 0 — — 5 mA
C
IN
(4)
Input Capacitance VI = 0, f = 1 MHz — 4 — pF
COUT
(4)
Output Capacitance VO = 0, f = 1 MHZ — 8 — pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36

IDT72V36104L10PF

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IC FIFO 131KX36 10NS 128QFP
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