16
FN6831.0
February 4, 2009
The LC output filter has a double pole at its resonant frequency
that causes rapid phase change. The R
3
modulator used in the
ISL62386 makes the LC output filter resemble a first order
system in which the closed loop stability can be achieved with
the recommended Type-II compensation network. Intersil
provides a PC-based tool that can be used to calculate
compensation network component values and help simulate
the loop frequency response.
LDO5 Linear Regulator
In addition to the two SMPS outputs, the ISL62386 also
provides two linear regulator outputs. LDO5 is fixed 5V LDO
output capable of sourcing 100mA continuous current.
When the output of SMPS2 is programmed to 5V, SMPS2 will
automatically take over the load of LDO5. This provides a
large power savings and boosts the efficiency. After
switchover to SMPS2, the LDO5 output current plus the
MOSFET drive current should not exceed 100mA in order to
guarantee the LDO5 output voltage in the range of 5V ±5%.
The total MOSFET drive current can be estimated by
Equation 16.
where Q
g
is the total gate charge of all the power MOSFET
in two SMPS regulators. Then the LDO5 output load current
should be less than (100mA - I
DRIVE
).
LDO3 Linear Regulator
ISL62386 includes LDO3 linear regulator whose output is fixed
3.3V. It can be independently enabled from both SMPS
channels. Logic high of LDO3EN will enable LDO3. LDO3 is
capable of sourcing 100mA continuous current. Currents in
excess of the limit will cause the LDO3 voltage to drop
dramatically, limiting the power dissipation.
Thermal Monitor and Protection
LDO3 and LDO5 can dissipate non-trivial power inside the
ISL62386 at high input-to-output voltage ratios and full load
conditions. To protect the silicon, ISL62386 continually
monitors the die temperature. If the temperature exceeds
+150°C, all outputs will be turned off to sharply curtail power
dissipation. The outputs will remain off until the junction
temperature has fallen below +135°C.
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to design a single-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following section. In addition to this guide, Intersil provides
complete reference designs that include schematics, bills of
materials, and example board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as
Equation 17:
The output inductor peak-to-peak ripple current is written as
Equation 18:
A typical step-down DC/DC converter will have an I
P-P
of
20% to 40% of the maximum DC output load current. The
value of I
P-P
is selected based upon several criteria such as
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding. The DC copper loss of the
inductor can be estimated by Equation 19:
Where I
LOAD
is the converter output DC current.
The copper loss can be significant so attention has to be given
to the DCR selection. Another factor to consider when choosing
the inductor is its saturation characteristics at elevated
temperatures. A saturated inductor could cause destruction of
circuit components, as well as nuisance OCP faults.
A DC/DC buck regulator must have output capacitance C
O
into which ripple current I
P-P
can flow. Current I
P-P
develops
out of the capacitor. These two voltages are written as
Equation 20:
and Equation 21:
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled
to reduce the total ESR until the required V
P-P
is achieved.
The inductance of the capacitor can cause a brief voltage dip
if the load transient has an extremely high slew rate. Low
inductance capacitors should be considered in this scenario.
A capacitor dissipates heat as a function of RMS current and
frequency. Be sure that I
P-P
is shared by a sufficient quantity
of paralleled capacitors so that they operate below the
maximum rated RMS current at F
SW
. Take into account that
the rated value of a capacitor can fade as much as 50% as
the DC voltage across it increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25x greater than the
(EQ. 16)
I
DRIVE
Q
g
F
SW
=
D
V
OUT
V
IN
---------------
=
(EQ. 17)
(EQ. 18)
I
PP
V
OUT
1D()
F
SW
L
--------------------------------------
=
(EQ. 19)
P
COPPER
I
LOAD
2
DCR=
ΔV
ESR
I
PP
E SR=
(EQ. 20)
ΔV
C
I
PP
8C
O
F
SW
-------------------------------
=
(EQ. 21)
ISL62386
17
FN6831.0
February 4, 2009
maximum input voltage, while a voltage rating of 1.5x is a
preferred rating. Figure 28 is a graph of the input capacitor
RMS ripple current, normalized relative to output load current,
as a function of duty cycle and is adjusted for converter
efficiency. The normalized RMS ripple current calculation is
written as Equation 22:
Where:
-I
MAX
is the maximum continuous I
LOAD
of the converter
- k is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a
percentage of I
MAX
(0% to 100%)
- D is the duty cycle that is adjusted to take into account
the efficiency of the converter which is written as:
Equation 23.
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum V
DS
rating that exceeds the sum of the
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low gate charge so that the
device spends the least amount of time dissipating power in
the linear region. Unlike the low-side MOSFET which has the
drain-source voltage clamped by its body diode during turn
off, the high-side MOSFET turns off with a V
DS
of
approximately V
IN
- V
OUT
, plus the spike across it. The
preferred low-side MOSFET emphasizes low r
DS(ON)
when
fully saturated to minimize conduction loss. It should be
noted that this is an optimal configuration of MOSFET
selection for low duty cycle applications (D < 50%). For
higher output, low input voltage solutions, a more balanced
MOSFET selection for high- and low-side devices may be
warranted.
For the low-side (LS) MOSFET, the power loss can be
assumed to be conductive only and is written as Equation 24:
For the high-side (HS) MOSFET, the conduction loss is
written as Equation 25:
For the high-side MOSFET, the switching loss is written as
Equation 26:
Where:
-I
VALLEY
is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
-I
PEAK
is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
-t
ON
is the time required to drive the device into
saturation
-t
OFF
is the time required to drive the device into cut-off
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as
Equation 27:
Where:
-Q
g
is the total gate charge required to turn on the
high-side MOSFET
- ΔV
BOOT
, is the maximum allowed voltage decay across
the boot capacitor each time the high-side MOSFET is
switched on
As an example, suppose the high-side MOSFET has a total
gate charge Q
g
, of 25nC at V
GS
= 5V, and a ΔV
BOOT
of
200mV. The calculated bootstrap capacitance is 0.125µF; for
a comfortable margin, select a capacitor that is double the
calculated capacitance. In this example, 0.22µF will suffice.
Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
(EQ. 22)
I
C
IN
RMS NORMALIZED,()
I
MAX
D1D()
Dk
2
12
--------------
+
I
MAX
-----------------------------------------------------------------------
=
D
V
OUT
V
IN
EFF
--------------------------
=
(EQ. 23)
FIGURE 28. NORMALIZED RMS INPUT CURRENT @ EFF = 1
NORMALIZED INPUT RMS RIPPLE CURRENT
DUTY CYCLE
00.1
0.2
0.3 0.4 0.6 0.7 0.8 0.9 1.00.5
0
0.12
0.24
0.36
0.48
0.60
k = 1
k = 0.75
k = 0.5
k = 0.25
k = 0
(EQ. 24)
P
CON_LS
I
LOAD
2
r
DS ON()_LS
1D()
(EQ. 25)
P
CON_HS
I
LOAD
2
r
DS ON()_HS
D=
(EQ. 26)
P
SW_HS
V
IN
I
VALLEY
t
ON
f
SW
2
-----------------------------------------------------------------
V
IN
I
PEAK
t
OFF
f
SW
2
-------------------------------------------------------------
+=
C
BOOT
Q
g
ΔV
BOOT
------------------------
=
(EQ. 27)
ISL62386
18
FN6831.0
February 4, 2009
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding. The ground plane layer
should have an island located under the IC, the
compensation components, and the FSET components. The
island should be connected to the rest of the ground plane
layer at one point.
Because there are two SMPS outputs and only one PGND
pin, the power train of both channels should be laid out
symmetrically. The line of bilateral symmetry should be
drawn through pins 4 and 21. This layout approach ensures
that the controller does not favor one channel over another
during critical switching decisions. Figure 30 illustrates one
example of how to achieve proper bilateral symmetry.
Signal Ground and Power Ground
The bottom of the ISL62386 TQFN package is the signal
ground (AGND) terminal for analog and logic signals of the
IC. The bottom pad is connected to AGND1 pin and AGND2
pin internally. Connect the AGND pad of the ISL62386 to the
island of ground plane under the IC using several vias for a
robust thermal and electrical conduction path. Connect the
input capacitors, the output capacitors, and the source of the
lower MOSFETs to the power ground (PGND) plane.
PGND (Pin 22)
This is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path.
VIN (Pin 20)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low
inductance path.
VCC (Pin 5)
For best performance, place the decoupling capacitor very
close to the VCC and AGND1 or AGND2 pin.
LDO3 (Pin 19) and LDO5 (Pin 21)
For best performance, place the decoupling capacitors very
close to LDO3 pin and PGND pin, LDO5 pin and PGND pin,
respectively, preferably on the same side of the PCB as the
ISL62386 IC.
EN (Pins 13 and 28) and PGOOD (Pin 1)
These are logic signals that are referenced to the AGND pin.
Treat them as typical logic signals.
OCSET (Pins 12 and 29) and ISEN (Pins 11 and 30)
For DCR current sensing, current-sense network, consisting
of R
OCSET
and C
SEN
, needs to be connected to the
inductor pads for accurate measurement. Connect R
OCSET
to the phase-node side pad of the inductor, and connect
C
SEN
to the output side pad of the inductor. The ISEN
resistor should also be connected to the output pad of the
inductor with a separate trace. Connect the OCSET pin to
the common node of node of R
OCSET
and C
SEN
.
For resistive current sensing, connect R
OCSET
from the
OCSET pin to the inductor side of the resistor pad. The ISEN
resistor should be connected to the V
OUT
side of the resistor
pad.
In both current-sense configurations, the resistor and
capacitor sensing elements, with the exclusion of the current
sense power resistor, should be placed near the
corresponding IC pin. The trace connections to the inductor
or sensing resistor should be treated as Kelvin connections.
FB (Pins 9 and 32), and VOUT (Pins 10 and 31)
The VOUT pin is used to generate the R
3
synthetic ramp
voltage and for soft-discharge of the output voltage during
shutdown events. This signal should be routed as close to
the regulation point as possible. The input impedance of the
FB pin is high, so place the voltage programming and loop
compensation components close to the VOUT, FB, and
AGND pins keeping the high impedance trace short.
FSET (Pins 2 and 8)
These pins require a quiet environment. The resistor R
FSET
and capacitor C
FSET
should be placed directly adjacent to
these pins. Keep fast moving nodes away from these pins.
FIGURE 29. TYPICAL POWER COMPONENT PLACEMENT
INDUCTOR
VIAS TO
GROUND
PLANE
VIN
VOUT
PHASE
NODE
GND
OUTPUT
CAPACITORS
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
SCHOTTKY
DIODE
HIGH-SIDE
MOSFETS
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
VIAS TO
GROUND
PLANE
INDUCTOR
HIGH-SIDE
MOSFETS
FIGURE 30. SYMMETRIC LAYOUT GUIDE
LINE OF SYMMETRY
PIN 5 (VCC)
PIN 20 (VIN)
L2
Ci
Co
L1
Ci
Co
U2L2
U1L1
ISL62386
PGND PLANE
PHASE PLANES
VOUT PLANES
VIN PLANE
ISL62386

ISL62386HRTZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers QD-OUTPUT SYSTEM CNTRLR 5X5 TQFN
Lifecycle:
New from this manufacturer.
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