7
FN6831.0
February 4, 2009
Pin Descriptions
PIN NAME FUNCTION
1
PGOOD Open-drain power-good status output. Connect to LDO5 through a 100k resistor. Output will be high when both the SMPSs outputs
are within the regulation window with no faults detected.
2
FSET2 Frequency control input for SMPS2. Connect a resistor to ground to program the switching frequency. A small ceramic capacitor
such as 10nF is necessary to parallel with this resistor to smooth the voltage.
3
FCCM Logic input to control efficiency mode. Logic high forces continuous conduction mode (CCM). Logic low allows full discontinuous
conduction mode (DCM). Float this pin for ultrasonic DCM operation.
4
AGND2 Analog ground of the SMPS2.
5
VCC Analog power supply input for reference voltages and currents. It is internally connected to the LDO5 output. Bypass to AGND1 or
AGND2 with a 1µF ceramic capacitor near the IC.
6
AGND1 Analog ground of the SMPS1. AGND1 and AGND2 are connected together internally.
7
LDO3EN Logic input for enabling and disabling the LDO3 linear regulator. Positive logic input.
8
FSET1 Frequency control input for SMPS1. Connect a resistor to ground to program the switching frequency. A small ceramic capacitor
such as 10nF is necessary to parallel with this resistor to smooth the voltage.
9
FB1 SMPS1 feedback input used for output voltage programming and regulation.
10 VOUT1
SMPS1 output voltage sense input. Used for soft-discharge.
11
ISEN1 SMPS1 current sense input. Used for overcurrent protection and R
3
regulation.
12
OCSET1 Input from current-sensing network, used to program the overcurrent shutdown threshold for SMPS1.
13
EN1 Logic input to enable and disable SMPS1. A logic high will enable SMPS1 immediately. A logic low will disable SMPS1. Floating this
input will delay SMPS1 start-up until after SMPS2 achieves regulation.
14, 27
NC No connection.
15
PHASE1 SMPS1 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS source, the
synchronous NMOS drain, and the output inductor for SMPS1.
16
UGATE1 High-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 switching FET.
17
BOOT1 SMPS1 bootstrap input for the switching NMOS gate drivers. Connect to PHASE1 with a 0.22µF ceramic capacitor.
18
LGATE1 Low-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 synchronous FET.
19
LDO3 LDO3 linear regulator output, providing up to 100mA. Bypass to ground with a 4.7µF ceramic capacitor.
20
VIN Feed-forward input for line voltage transient compensation. Connect to the power train input voltage.
21
LDO5 5V linear regulator output, providing up to 100mA before switchover to SMPS2. Bypass to ground with a 4.7µF ceramic capacitor.
22
PGND Power ground for SMPS1 and SMPS2. This provides a return path for synchronous FET switching currents.
23
LGATE2 Low-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 synchronous FET.
24
BOOT2 SMPS2 bootstrap input for the switching NMOS gate drivers. Connect to PHASE2 with a 0.22µF ceramic capacitor.
25
UGATE2 High-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 switching FET.
26
PHASE2 SMPS2 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS source, the
synchronous NMOS drain, and the output inductor for SMPS2.
28
EN2 Logic input to enable and disable SMPS2. A logic high will enable SMPS2 immediately. A logic low will disable SMPS2. Floating this
input will delay SMPS2 start-up until after SMPS1 achieves regulation.
29
OCSET2 Input from current-sensing network, used to program the over-current shutdown threshold for SMPS2.
30
ISEN2 SMPS2 current sense input. Used for overcurrent protection and R
3
regulation.
31
VOUT2 SMPS2 output voltage sense input. Used for soft-discharge and switchover to LDO5 output.
32
FB2 SMPS2 feedback input used for output voltage programming and regulation.
Bottom
Pad
Thermal pad. Connected to AGND internally.
ISL62386
