CYD04S72V
CYD09S72V
CYD18S72V
FLEx72™ 3.3 V 64 K/128 K/256 K × 72
Synchronous Dual-Port RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number : 38-06069 Rev. *M Revised October 12, 2011
Features
■ True dual-ported memory cells that allow simultaneous access
of the same memory location
■ Synchronous pipelined operation
■ Family of 4 Mbit, 9 Mbit, and 18 Mbit devices
■ Pipelined output mode allows fast operation
■ 0.18-micron complmentary metal oxide semiconductor
(CMOS) for optimum speed and power
■ High-speed clock to data access
■ 3.3 V low power
❐ Active as low as 225 mA (typ)
❐ Standby as low as 55 mA (typ)
■ Mailbox function for message passing
■ Global master reset
■ Separate byte enables on both ports
■ Commercial and industrial temperature ranges
■ IEEE 1149.1-compatible joint test action group (JTAG)
boundary scan
■ 484-ball fine-pitch ball grid array (FBGA) (1-mm pitch)
■ Pb-free packaging available
■ Counter wrap around control
❐ Internal mask register controls counter wrap-around
❐ Counter-interrupt flags to indicate wrap-around
❐ Memory block retransmit operation
■ Counter readback on address lines
■ Mask register readback on address lines
■ Dual chip enables on both ports for easy depth expansion
■ Seamless migration to next generation dual-port family
Functional Description
The FLEx72 family includes 4 Mbit, 9 Mbit and 18 Mbit pipelined,
synchronous, true dual-port static RAMs that are high-speed,
low-power 3.3 V CMOS. Two ports are provided, permitting
independent, simultaneous access to any location in memory.
The result of writing to the same location by more than one port
at the same time is undefined. Registers on control, address, and
data lines allow for minimal set-up and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter will increment the address internally (more
details to follow). The internal write pulse width is independent of
the duration of the R/W
input signal. The internal write pulse is
self-timed to allow the shortest possible cycle times.
A HIGH on CE0
or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT
)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CYD18S72V device have limited features. Please see
Table 3 on page 8 for details.
Seamless Migration to Next-Generation Dual-Port
Family
Cypress offers a migration path for all devices to the
next-generation devices in the Dual-Port family with a compatible
footprint. Please contact Cypress Sales for more details
.
Table 1. Product Selection Guide
Density
4-Mbit
(64K x 72)
9-Mbit
(128K x 72)
18-Mbit
(256K x 72)
Part number CYD04S72V CYD09S72V CYD18S72V
Max. speed (MHz) 167 133 133
Max. access time—clock to data (ns) 4.0 4.4 5.0
Typical operating current (mA) 225 350 410
Package 484-ball FBGA
23 mm x 23 mm
484-ball FBGA
23 mm x 23 mm
484-ball FBGA
23 mm x 23 mm
