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CYD04S72V-167BBC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
CYD04S72V
CYD09S72V
CYD18S72V
Document Number : 38-06069 Rev. *M Page 13 of 30
Maximum Ratings
[35]
(Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested)
Storage temperature............................... –65 °C to + 150 °C
Ambient temperature with
power applied .......................................... –55 °C to + 125 °C
Supply voltage to ground potential ..............–0.5 V to + 4.6 V
DC Voltage Applied to
Outputs in High-Z state........................ –0.5 V to V
DD
+ 0.5 V
DC input voltage............................. –0.5 V to V
DD
+ 0.5 V
[37]
Output current into outputs (LOW) ..............................20 mA
Static discharge voltage...........................................> 2000 V
(JEDEC JESD22-A114-2000B)
Latch-up current .....................................................> 200 mA
Operating Range
Range
Ambient
Temperature
V
DD
V
CORE
[36]
Commercial 0 °C to +70 °C 3.3 V ± 165 mV 1.8 V ± 100 mV
Industrial –40 °C to +85 °C 3.3 V ± 165 mV 1.8 V ± 100mV
Electrical Characteristics Over the Operating Range
Parameter Description Part No.
–167 –133 –100
Unit
Min Typ Max Min Typ Max Min Typ Max
V
OH
Output HIGH voltage (V
DD
= Min., I
OH
=
–4.0 mA)
2.4 – – 2.4 – – 2.4 – – V
V
OL
Output LOW voltage (V
DD
= Min., I
OL
= +4.0
mA)
––0.4––0.4– –0.4V
V
IH
Input HIGH voltage 2.0 – – 2.0 – – 2.0 – – V
V
IL
Input LOW voltage – – 0.8 – – 0.8 – – 0.8 V
I
OZ
Output leakage current –10 – 10 –10 – 10 –10 – 10 A
I
IX1
Input leakage current except TDI, TMS,
MRST
–10 – 10 –10 – 10 –10 – 10 A
I
IX2
Input leakage current TDI, TMS, MRST –0.1 – 1.0 –0.1 – 1.0 –0.1 – 1.0 mA
I
CC
Operating current
(V
DD
= Max.,I
OUT
= 0 mA),
outputs disabled
CYD04S72V – 225 300 – – – – – – mA
CYD09S72V – – – – 350 500 – – –
CYD18S72V – – – – 410 580 – 315 450 mA
I
SB1
Standby current
(both ports TTL level)
CE
L
and CE
R
V
IH
, f = f
MAX
CYD04S72V – 90 115 – – – – mA
CYD09S72V – – – – 105 150 – – –
I
SB2
Standby current
(one port TTL level)
CE
L
| CE
R
V
IH
, f = f
MAX
CYD04S72V – 160 210 – – – – mA
CYD09S72V – – – – 266 380 – – –
I
SB3
Standby current (both ports
CMOS level) CE
L
and CE
R
V
DD
– 0.2V, f = 0
CYD04S72V – 55 75 – – – – mA
CYD09S72V – – – – 55 75 – – –
I
SB4
Standby current
(one port CMOS level)
CE
L
| CE
R
V
IH
, f = f
MAX
CYD04S72V – 160 210 – – – – mA
CYD09S72V – – – – 224 320 – –
I
SB5
Operating current (VDDIO
= Max, Iout = 0 mA, f = 0)
outputs disabled
CYD18S72V – – – – 75 – – 75 mA
I
CORE
[36]
Core operating current for (V
DD
= Max.,
I
OUT
= 0 mA), outputs disabled
–00–00 – 0 0mA
Notes
35. The voltage on any input or I/O pin can not exceed the power pin during power-up.
36. This family of Dual-Ports does not use VCORE, and these pins are internally NC. The next generation Dual-Port family, the FLEx72-E™, will use VCORE of 1.5 V or
1.8 V. Please contact local Cypress FAE for more information.
37. Pulse width < 20 ns.
CYD04S72V
CYD09S72V
CYD18S72V
Document Number : 38-06069 Rev. *M Page 14 of 30
AC Test Load and Waveforms
Capacitance
[38]
Part# Parameter Description Test Conditions Max Unit
CYD04S72V
CYD09S72V
C
IN
Input capacitance T
A
= 25 °C, f = 1 MHz,
V
DD
= 3.3 V
20 pF
C
OUT
Output capacitance 10
[39]
pF
CYD18S72V C
IN
Input capacitance 40 pF
C
OUT
Output capacitance 20 pF
Switching Characteristics Over the Operating Range
Parameter Description
–167 –133 –100
UnitCYD04S72V CYD09S72V CYD18S72V CYD18S72V
Min Max Min Max Min Max Min Max
f
MAX2
Maximum operating frequency – 167 – 133 – 133 – 100 MHz
t
CYC2
Clock cycle time 6.0 – 7.5 – 7.5 – 10 – ns
t
CH2
Clock HIGH time 2.7–3.0–3.4–4.5– ns
t
CL2
Clock LOW time 2.7–3.0–3.4–4.5–ns
t
R
[40]
Clock rise time –2.0–2.0–2.0–3.0ns
t
F
[40]
Clock fall time – 2.0 – 2.0 – 2.0 – 3.0 ns
t
SA
Address set-up time 2.3–2.5–2.2–2.7– ns
t
HA
Address hold time 0.6 – 0.6 – 1.0 – 1.0 – ns
t
SB
Byte select set-up time 2.3 – 2.5 – 2.2 – 2.7 – ns
t
HB
Byte select hold time 0.6–0.6–1.0–1.0–ns
t
SC
Chip enable set-up time 2.3 – 2.5 – NA – NA – ns
t
HC
Chip enable hold time 0.6 – 0.6 – NA – NA – ns
t
SW
R/W set-up time 2.3–2.5–2.2–2.7– ns
t
HW
R/W hold time 0.6–0.6–1.0–1.0– ns
t
SD
Input data set-up time 2.3 – 2.5 – 2.2 – 2.7 – ns
t
HD
Input data hold time 0.6–0.6–1.0–1.0– ns
Notes
38. C
OUT
also references C
I/O.
39. Except INT and CNTINT which are 20 pF.
40. Except JTAG signal (t
R
and t
F
< 10 ns max).
R1 = 590
R2 = 435
C = 5 pF
(b) Three-state Delay (Load 2)
90%
10%
3.0 V
Vss
90%
10%
<2ns <2ns
ALL INPUT PULSES
3.3 V
V
TH
= 1.5 V
R = 50
Z
0
= 50
(a) Normal Load (Load 1)
C = 10 pF
OUTPUT
OUTPUT
CYD04S72V
CYD09S72V
CYD18S72V
Document Number : 38-06069 Rev. *M Page 15 of 30
t
SAD
ADS set-up time 2.3 – 2.5 – NA – NA – ns
t
HAD
ADS hold time 0.6 – 0.6 – NA – NA – ns
t
SCN
CNTEN set-up time 2.3 – 2.5 – NA – NA – ns
t
HCN
CNTEN hold time 0.6 – 0.6 – NA – NA – ns
t
SRST
CNTRST set-up time 2.3 – 2.5 – NA – NA – ns
t
HRST
CNTRST hold time 0.6 – 0.6 – NA – NA – ns
t
SCM
CNT/MSK set-up time 2.3 – 2.5 – NA – NA – ns
t
HCM
CNT/MSK hold time 0.6 – 0.6 – NA – NA – ns
t
OE
Output enable to data valid – 4.0 – 4.4 – 5.5 – 5.5 ns
t
OLZ
[41, 42]
OE to Low Z 0–0–0–0–ns
t
OHZ
[41, 42]
OE to High Z 0 4.0 0 4.4 0 5.5 0 5.5 ns
t
CD2
Clock to data valid – 4.0 – 4.4 – 5.0 – 5.2 ns
t
CA2
Clock to counter address valid – 4.0 – 4.4 – NA – NA ns
t
CM2
Clock to mask register readback
valid
–4.0–4.4–NA–NAns
t
DC
Data output hold after clock
HIGH
1.0–1.0–1.0–1.0– ns
t
CKHZ
[41, 42]
Clock HIGH to output High Z 0 4.0 0 4.4 0 4.7 0 5.0 ns
t
CKLZ
[41, 42]
Clock HIGH to output Low Z 1.0 4.0 1.0 4.4 1.0 4.7 1.0 5.0 ns
t
SINT
Clock to INT set time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns
t
RINT
Clock to INT reset time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns
t
SCINT
Clock to CNTINT set time 0.5 5.0 0.5 5.7 NA NA NA NA ns
t
RCINT
Clock to CNTINT reset time 0.5 5.0 0.5 5.7 NA NA NA NA ns
Port to Port Delays
t
CCS
Clock to clock skew 5.2 – 6.0 – 5.7 – 8.0 – ns
Master Reset Timing
t
RS
Master reset pulse width 5.0 – 5.0 – 5.0 – 5.0 – cycles
t
RSS
Master reset set-up time 6.0 – 6.0 – 6.0 – 8.5 – ns
t
RSR
Master reset recovery time 5.0 – 5.0 – 5.0 – 5.0 – cycles
t
RSF
Master Reset to outputs inactive – 10.0 – 10.0 – 10.0 – 10.0 ns
t
RSCNTINT
Master reset to counter interrupt
flag reset time
– 10.0 – 10.0 – NA – NA ns
Notes
41. This parameter is guaranteed by design, but is not production tested.
42. Test conditions used are Load 2.
Switching Characteristics Over the Operating Range (continued)
Parameter Description
–167 –133 –100
UnitCYD04S72V CYD09S72V CYD18S72V CYD18S72V
Min Max Min Max Min Max Min Max
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CYD04S72V-167BBC

Mfr. #:
Buy CYD04S72V-167BBC
Manufacturer:
Cypress Semiconductor
Description:
SRAM 4MB (64Kx72) 3.3v 167MHz Sync SRAM
Lifecycle:
New from this manufacturer.
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