CYD04S72V
CYD09S72V
CYD18S72V
Document Number : 38-06069 Rev. *M Page 5 of 30
Pin Definitions
Left Port Right Port Description
A
0L
–A
17L
A
0R
–A
17R
Address inputs.
BE
0L
–BE
7L
BE
0R
–BE
7R
Byte enable inputs. Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
BUSY
L
[11,12]
BUSY
R
[11,12]
Port busy output. When the collision is detected, a BUSY is asserted.
C
L
C
R
Input clock signal.
CE0
L
[13]
CE0
R
[13]
Active low chip enable input.
CE1
L
[14]
CE1
R
[14]
Active high chip enable input.
DQ
0L
–DQ
71L
DQ
0R
–DQ
71R
Data bus input/output.
OE
L
OE
R
Output enable input. This asynchronous signal must be asserted LOW to enable the
DQ data pins during Read operations.
INT
L
INT
R
Mailbox interrupt flag output. The mailbox permits communications between ports.
The upper two memory locations can be used for message passing. INT
L
is asserted
LOW when the right port writes to the mailbox location of the left port, and vice versa.
An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox.
LowSPD
L
[11,15]
LowSPD
R
[11,15]
Port low speed select input. When operating at less than 100 MHz, the LowSPD
disables the port DLL.
PORTSTD[1:0]
L
[11,15
]
PORTSTD[1:0]
R
[11,15
]
Port address/control/data i/o standard select input.
R/W
L
R/W
R
Read/write enable input. Assert this pin LOW to write to, or HIGH to Read from the
dual-port memory array.
READY
L
[11,12]
READY
R
[11,12]
Port ready output. This signal will be asserted when a port is ready for normal
operation.
CNT/MSK
L
[14]
CNT/MSK
R
[14]
Port counter/mask select input. Counter control input.
ADS
L
[13]
ADS
R
[13]
Port counter address load strobe input. Counter control input.
CNTEN
L
[13]
CNTEN
R
[13]
Port counter enable input. Counter control input.
CNTRST
L
[14]
CNTRST
R
[14]
Port counter reset input. Counter control input.
CNTINT
L
[16]
CNTINT
R
[16]
Port counter interrupt output. This pin is asserted LOW when the unmasked portion
of the counter is incremented to all “1s”.
WRP
L
[11,17]
WRP
R
[11,17]
Port counter wrap input. After the burst counter reaches the maximum count, if WRP
is low, the unmasked counter bits will be set to 0. If high, the counter will be loaded with
the value stored in the mirror register.
RET
L
[11,17]
RET
R
[12,17]
Port counter retransmit input. Counter control input.
FTSEL
L
[11,17]
FTSEL
R
[11,17]
Flow-through select. Use this pin to select Flow-Through mode. When is de-asserted,
the device is in pipelined mode.
VREF
L
[11,15]
VREF
R
[11,15]
Port external high-speed io reference input.
Notes
11. This ball will represent a next generation Dual-Port feature. For more information about this feature, contact Cypress Sales.
12. Leave this ball unconnected. For more information about this feature, contact Cypress Sales.
13. These balls are not applicable for CYD18S72V device. They need to be tied to VSS.
14. These balls are not applicable for CYD18S72V device. They need to be tied to VDDIO.
15. Connect this ball to VSS. For more information about this next generation Dual-Port feature, contact Cypress Sales.
16. These balls are not applicable for CYD18S72V device. They need to be no connected.
17. Connect this ball to VDDIO. For more information about this next generation Dual-Port feature contact Cypress Sales
