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CYD04S72V-167BBC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
CYD04S72V
CYD09S72V
CYD18S72V
Document Number : 38-06069 Rev. *M Page 16 of 30
JTAG Timing Characteristics
Parameter Description
CYD04S72V
CYD09S72V
CYD18S72V
Unit
–167/–133/–100
Min Max
f
JTAG
Maximum JTAG TAP controller frequency – 10 MHz
t
TCYC
TCK clock cycle time 100 – ns
t
TH
TCK clock HIGH time 40 – ns
t
TL
TCK clock LOW time 40 – ns
t
TMSS
TMS set-up to TCK clock rise 10 – ns
t
TMSH
TMS hold after TCK clock rise 10 – ns
t
TDIS
TDI set-up to TCK clock rise 10 – ns
t
TDIH
TDI hold after TCK clock rise 10 – ns
t
TDOV
TCK clock LOW to TDO valid – 30 ns
t
TDOX
TCK clock LOW to TDO invalid 0 – ns
Switching Waveforms
Test Clock
Test Mode Select
TCK
TMS
Test Data-In
TDI
Test Data-Out
TDO
t
TCYC
t
TMSH
t
TL
t
TH
t
TMSS
t
TDIS
t
TDIH
t
TDOX
t
TDOV
CYD04S72V
CYD09S72V
CYD18S72V
Document Number : 38-06069 Rev. *M Page 17 of 30
Figure 4. Master Reset
Figure 5. Read Cycle
[43, 44, 45, 46, 47]
Notes
43.
CE is internal signal. CE = LOW if CE
0
= LOW and CE
1
= HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
44. OE
is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
45. ADS
= CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
46. The output is disabled (high-impedance state) by CE
= V
IH
following the next rising edge of the clock.
47. Addresses do not have to be accessed sequentially since ADS
= CNTEN = V
IL
with CNT/MSK = V
IH
constantly loads the address on the rising edge of the CLK.
Numbers are for reference only.
Switching Waveforms (continued)
MRST
t
RSR
t
RS
INACTIVE
ACTIVE
TMS
TDO
INT
CNTINT
t
RSF
t
RSS
ALL
ADDRESS/
DATA
LINES
ALL
OTHER
INPUTS
t
CH2
t
CL2
t
CYC2
t
SC
t
HC
t
SW
t
HW
t
SA
t
HA
A
n
A
n+1
CLK
CE
R/W
ADDRESS
DATA
OUT
OE
A
n+2
A
n+3
t
SC
t
HC
t
OHZ
t
OE
t
OLZ
t
DC
t
CD2
t
CKLZ
Q
n
Q
n+1
Q
n+2
1 Latency
BE0
–BE7
t
SB
t
HB
CYD04S72V
CYD09S72V
CYD18S72V
Document Number : 38-06069 Rev. *M Page 18 of 30
Figure 6. Bank Select Read
[48, 49]
Figure 7. Read-to-Write-to-Read (OE = LOW)
[47, 50, 51, 52, 53]
Notes
48. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx72 device from this data sheet. ADDRESS
(B1)
= ADDRESS
(B2)
.
49. ADS
= CNTEN = BE0 – BE7 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
50. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
51. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
52. CE
0
= OE = BE0 – BE7 = LOW; CE
1
= R/W = CNTRST = MRST = HIGH.
53. CE
0
= BE0 – BE7 = R/W = LOW; CE
1
= CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Switching Waveforms (continued)
Q
3
Q
1
Q
0
Q
2
A
0
A
1
A
2
A
3
A
4
A
5
Q
4
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
t
SC
t
HC
t
SA
t
HA
t
SC
t
HC
t
SC
t
HC
t
SC
t
HC
t
CKHZ
t
DC
t
DC
t
CD2
t
CKLZ
t
CD2
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
CH2
t
CL2
t
CYC2
CLK
ADDRESS
(B1)
CE
(B1)
DATA
OUT(B2)
DATA
OUT(B1)
ADDRESS
(B2)
CE
(B2)
CLK
CE
R/W
ADDRESS
DATA
IN
DATA
OUT
t
HC
t
SC
t
HW
t
SW
t
HA
t
SA
t
HW
t
SW
t
CD2
t
CKHZ
t
SD
t
HD
NO OPERATION
WRITE
READ
A
n
A
n+1
A
n+2
A
n+2
D
n+2
A
n+2
A
n+3
Q
n
t
CL2
t
CH2
t
CYC2
t
DC
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CYD04S72V-167BBC

Mfr. #:
Buy CYD04S72V-167BBC
Manufacturer:
Cypress Semiconductor
Description:
SRAM 4MB (64Kx72) 3.3v 167MHz Sync SRAM
Lifecycle:
New from this manufacturer.
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