9397 750 14325 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 9 December 2004 12 of 55
Philips Semiconductors
SAA7128H; SAA7129H
Digital video encoder
Alternating phase reset in accordance with SECAM standard is carried out automatically.
During vertical blanking, the so-called ‘bottle pulses’ are not provided.
7.6 Output interface/DACs
In the output interface, encoded Yand C signals are converted from digital-to-analog in a
10-bit resolution. Yand C signals are also combined in a 10-bit CVBS signal.
The CVBS output occurs with the same processing delay (equal to 82 LLC clock periods,
measured from MP input to the analog outputs) as the Y, C and RGB outputs. Absolute
amplitude at the input of the DAC for CVBS is reduced by
15
⁄
16
with respect to Yand C
DACs to make maximum use of conversion ranges.
Red, green and blue signals are also converted from digital-to-analog, each providing a
9-bit resolution.
Outputs of the DACs can be set together via software control to minimum output voltage
(approximately 0.2 V DC) for either purpose. Alternatively, the buffers can be switched into
3-state output condition; this allows for a ‘wired AND’ configuration with other 3-state
outputs and can also be used as a power-save mode.
7.7 Synchronization
The synchronization of the SAA7128H; SAA7129H is able to operate in two modes; slave
mode and master mode.
In master mode, see Figure 19, the circuit generates all necessary timings in the video
signal itself, and it can provide timing signals at the RCV1 and RCV2 ports. In slave mode,
it accepts timing information either from the RCV pins or from the embedded timing data
of the
ITU-R BT.656
data stream.
For the SAA7128H; SAA7129H, the only difference between master and slave mode is
that it ignores the timing information at its inputs in master mode. Thus, if in slave mode,
any timing information is missing, the IC will continue running free without a visible effect.
But there must not be any additional pulses (with wrong phase) because the circuit will not
ignore them.
In slave mode, see Figure 18, an interface circuit decides which signal is expected at the
RCV1 port and which information is taken from its active slope. The polarity can be
chosen. If PRCV1 is logic 0, the rising slope will be active.
The signal can be:
• A Vertical Sync (VS) pulse; the active slope sets the vertical phase
• An odd/even signal; the active slope sets the vertical phase, the internal field flag to
odd and optionally sets the horizontal phase
• A Field Sequence (FSEQ) signal; it marks the first field of the 4 (NTSC) or 8 (PAL) or
12 (SECAM) field sequences; in addition to the odd/even signal, it also sets the PAL
phase and optionally defines the subcarrier phase.
On the RCV2 port, the IC can provide a horizontal pulse with programmable start and stop
phase; this pulse can be inhibited in the vertical blanking period to build up, for example, a
composite blanking signal.
