9397 750 14325 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 9 December 2004 31 of 55
Philips Semiconductors
SAA7128H; SAA7129H
Digital video encoder
Table 60: Selection of field length control
FLC1 FLC0 Description
0 0 interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default
value after reset
0 1 non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
1 0 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
11
Table 61: Subaddress 6Fh
Bit Symbol Description
7 CCEN1 these 2 bits enable individual line 21 encoding; see
Table 62
6 CCEN0
5 TTXEN 0 = disables teletext insertion; default state after reset,
1 = enables teletext insertion.
4 SCCLN4 these 5 bits select the actual line where closed caption or extended data
are encoded:
3 SCCLN3 line = (SCCLN[4:0] + 4) for M-systems
line = (SCCLN[4:0] + 1) for other systems.
2 SCCLN2
1 SCCLN1
0 SCCLN0
Table 62: Selection of line 21 encoding
CCEN1 CCEN0 Line 21 encoding
0 0 line 21 encoding off; default value after reset
0 1 enables encoding in field 1 (odd)
1 0 enables encoding in field 2 (even)
1 1 enables encoding in both fields
Table 63: Subaddress 70h
Bit Symbol Description
7 to 0 RCV2S[7:0] these are the 8 LSBs of the 11-bit code that determines the start of the
output signal on the RCV2 pin; the 3 MSBs of the 11-bit code are held at
subaddress 72h; see
Table 65; values above 1715 (FISE = 1)
or 1727 (FISE = 0) are not allowed; leading sync slope at CVBS output
coincides with leading slope of RCV2 out at RCV2S = 49h
Table 64: Subaddress 71h
Bit Symbol Description
7 to 0 RCV2E[7:0] these are the 8 LSBs of the 11-bit code that determines the end of the
output signal on the RCV2 pin; the 3 MSBs of the 11-bit code are held at
subaddress 72h; see
Table 65; values above 1715 (FISE = 1)
or 1727 (FISE = 0) are not allowed; leading sync slope at CVBS output
coincides with trailing slope of RCV2 out at RCV2E = 49h
