SAA7129H/V1,557 Datasheet SAA7129H/V1,518, SAA7129H/V1,557 | P28-P30

Product data sheet Rev. 03 — 9 December 2004 28 of 55

Philips Semiconductors

SAA7128H; SAA7129H

Digital video encoder

[1] Examples:

a) NTSC-M: f

= 227.5, f

llc

= 1716 → FSC = 569408543 (21F07C1Fh).

b) PAL-B/G: f

= 283.7516, f

llc

= 1728 → FSC = 705268427 (2A098ACBh).

c) SECAM: f

= 274.304, f

llc

= 1728 → FSC = 681786290 (28A33BB2h).

64h FSC[15:08] f

= subcarrier frequency (in multiples of line frequency)

llc

= clock frequency (in multiples of line frequency).

65h FSC[23:16]

FSC = round

[1]

66h FSC[31:24]

Table 49: Subaddress 67h

Bit Symbol Description

7 to 0 L21O[07:00] ﬁrst byte of captioning data, odd ﬁeld; LSB of the byte is encoded

immediately after run-in and framing code, the MSB of the byte has to

carry the parity bit, in accordance with the deﬁnition of line 21

encoding format

Table 50: Subaddress 68h

Bit Symbol Description

7 to 0 L21O[17:10] second byte of captioning data, odd ﬁeld; the MSB of the byte has to

carry the parity bit, in accordance with the deﬁnition of line 21

encoding format

Table 51: Subaddress 69h

Bit Symbol Description

7 to 0 L21E[07:00] ﬁrst byte of extended data, even ﬁeld; LSB of the byte is encoded

immediately after run-in and framing code, the MSB of the byte has to

carry the parity bit, in accordance with the deﬁnition of line 21

encoding format

Table 52: Subaddress 6Ah

Bit Symbol Description

7 to 0 L21E[17:10] second byte of extended data, even ﬁeld; the MSB of the byte has to

carry the parity bit, in accordance with the deﬁnition of line 21

encoding format

Table 53: Subaddress 6Bh

Bit Symbol Description

7 SRCV11 these 2 bits deﬁne signal type on pin RCV1; see

Table 54

6 SRCV10

5 TRCV2 0 = horizontal synchronization is taken from RCV1 port (at bit

SYMP = LOW) or from decoded frame sync of

ITU-R BT.656

input (at

bit SYMP = HIGH); default state after reset,

1 = horizontal synchronization is taken from RCV2 port (at bit

SYMP = LOW).

Table 48: Subaddresses 63h to 66h

…continued

Address Byte Description

llc

---------





Product data sheet Rev. 03 — 9 December 2004 29 of 55

Philips Semiconductors

SAA7128H; SAA7129H

Digital video encoder

4 ORCV1 0 = pin RCV1 is switched to input; default state after reset,

1 = pin RCV1 is switched to output.

3 PRCV1 0 = polarity of RCV1 as output is active HIGH, rising edge is taken

when input; default state after reset,

1 = polarity of RCV1 as output is active LOW, falling edge is taken

when input.

2 CBLF when CBLF = 0:

If ORCV2 = 1, pin RCV2 provides an HREF signal (horizontal

reference pulse that is deﬁned by RCV2S and RCV2E, also during

vertical blanking interval); default state after reset

If ORCV2 = 0 and bit SYMP = 0, signal input to RCV2 is used for

horizontal synchronization only (if TRCV2 = 1); default state after

reset.

when CBLF = 1:

If ORCV2 = 1, pin RCV2 provides a ‘composite-blanking-not’ signal,

for example a reference pulse that is deﬁned by RCV2S and

RCV2E, excluding vertical blanking interval, which is deﬁned by FAL

and LAL

If ORCV2 = 0 and bit SYMP = 0, signal input to RCV2 is used for

horizontal synchronization (if TRCV2 = 1) and as an internal

blanking signal.

1 ORCV2 0 = pin RCV2 is switched to input; default state after reset,

1 = pin RCV2 is switched to output.

0 PRCV2 0 = polarity of RCV2 as output is active HIGH, rising edge is taken

when input, respectively; default state after reset,

1 = polarity of RCV2 as output is active LOW, falling edge is taken

when input, respectively.

Table 54: Selection of the signal type on pin RCV1

SRCV11 SRCV10 RCV1 Function

0 0 VS Vertical Sync each ﬁeld; default state after reset

0 1 FS Frame Sync (odd/even).

1 0 FSEQ Field Sequence, vertical sync every fourth ﬁeld (PAL = 0),

eighth ﬁeld (PAL = 1) or twelfth ﬁeld (SECAM = 1).

1 1 - not applicable

Table 55: Subaddress 6Ch

Bit Symbol Description

7 to 0 HTRIG[7:0] These are the 8 LSBs of the 11-bit code that sets the horizontal trigger

phase related to the signal on RCV1 or RCV2 input. The 3 MSBs are held

in subaddress 6Dh; see

Table 56. Values above 1715 (FISE = 1) or

1727 (FISE = 0) are not allowed. Increasing HTRIG[10:0] decreases

delays of all internally generated timing signals. Reference mark: analog

output horizontal sync (leading slope) coincides with active edge of RCV

used for triggering at HTRIG[10:0] = 4Fh (79).

Table 53: Subaddress 6Bh

…continued

Bit Symbol Description

Product data sheet Rev. 03 — 9 December 2004 30 of 55

Philips Semiconductors

SAA7128H; SAA7129H

Digital video encoder

Table 56: Subaddress 6Dh

Bit Symbol Description

7 HTRIG10 these are the 3 MSBs of the horizontal trigger phase code; see

Table 55

6 HTRIG9

5 HTRIG8

4 VTRIG4 sets the vertical trigger phase related to signal on RCV1 input; increasing

VTRIG decreases delays of all internally generated timing signals,

measured in half lines; variation range of VTRIG[4:0] = 0 to 31 (1Fh)

3 VTRIG3

2 VTRIG2

1 VTRIG1

0 VTRIG0

Table 57: Subaddress 6Eh

Bit Symbol Description

7 SBLBN 0 = vertical blanking is deﬁned by programming of FAL and LAL; default

state after reset,

1 = vertical blanking is forced in accordance with

ITU-R BT.624

(50 Hz) or

RS170A

(60 Hz).

6 BLCKON 0 = encoder in normal operation mode,

1 = output signal is forced to blanking level; default state after reset.

5 PHRES1 these 2 bits select the phase reset mode of the color subcarrier

generator; see

Table 58

4 PHRES0

3 LDEL1 these 2 bits select the delay on luminance path with reference to

chrominance path; see

Table 59

2 LDEL0

1 FLC1 these 2 bits select ﬁeld length control; see

Table 60

0 FLC0

Table 58: Selection of phase reset mode

PHRES1 PHRES0 Description

0 0 no reset or reset via RTCI from SAA7113 or SAA7118 if bit RTCE = 1;

default value after reset

0 1 reset every two lines or SECAM speciﬁc if bit SECAM = 1

1 0 reset every eight ﬁelds

1 1 reset every four ﬁelds

Table 59: Selection of luminance path delay

LDEL1 LDEL0 Luminance path delay

0 0 no luminance delay; default value after reset

0 1 1 LLC luminance delay

1 0 2 LLC luminance delay

1 1 3 LLC luminance delay

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P55

SAA7129H/V1,557

Mfr. #:

Buy SAA7129H/V1,557

Manufacturer:

NXP Semiconductors

Description:

IC DIGITAL VIDEO ENCODER 44-QFP

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

SAA7129H/V1,557

SAA7129H/V1,557

Products related to this Datasheet