LTC2360/LTC2361/LTC2362
14
236012fa
APPLICATIONS INFORMATION
OVERVIEW
The LTC2360/LTC2361/LTC2362 use a successive ap-
proximation algorithm and internal sample-and-hold circuit
to convert an analog signal to a 12-bit serial output. All
devices operate from a single 2.35V to 3.6V supply. The
conversion time of the devices is controlled by an internal
oscillator, which allows the LTC2360/LTC2361/LTC2362
to sample at a rate of 100ksps, 250ksps and 500ksps
respectively.
The LTC2360/LTC2361/LTC2362 contain a 12-bit, switched-
capacitor ADC, a sample-and-hold, a serial interface (see
Block Diagram) and are available in tiny 6- or 8-lead
TSOT-23 packages.
The S6 package of the LTC2360/LTC2361/LTC2362 uses
V
DD
as the reference and has an analog input range of 0V
to V
DD
. The ADC samples the analog input with respect to
GND and outputs the result through the serial interface.
The TS8 package provides two additional pins: a reference
pin, V
REF
, and an output supply pin, OV
DD
. The ADC can
operate with reduced spans down to 1.4V and achieve
342V resolution. OV
DD
controls the output swing of the
digital output pin, SDO, and allows the device to com-
municate with 1.8V, 2.5V or 3V digital systems.
SERIAL INTERFACE
The LTC2360/LTC2361/LTC2362 communicate with micro-
controllers, DSPs and other external circuitry via a 3-wire
interface. Figure 10 shows the operating sequence of the
serial interface.
Data Transfer
A rising CONV edge starts a conversion and disables SDO.
After the conversion, the ADC automatically goes into sleep
mode, drawing only leakage current.
CONV going low enables SDO and clocks out the MSB bit,
B11. SCK then synchronizes the data transfer with each
bit being transmitted on the falling SCK edge and can be
captured on the rising SCK edge. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefi nitely (see Figure 10). For
example, 16-clocks at SCK will produce the 12-bit data
and four trailing zeros on SDO.
SLEEP MODE
The LTC2360/LTC2361/LTC2362 enter sleep mode to save
power after each conversion if CONV remains high. In sleep
mode, all bias currents are shut down and only leakage
currents remain (about 0.1µA). The sample-and-hold is
in hold mode while the ADC is in sleep mode. The ADC
returns to sample mode after the falling edge of CONV
during power-up (see Figure 10).
Exiting Sleep Mode and Power-Up Time
By taking CONV low, the ADC powers up and acquires an
input signal completely after the aquisition time (t
ACQ
).
After t
ACQ
, the ADC can perform a conversion as described
in the Serial Interface section (see Figure 10).
1
RECOMMENDED HIGH OR LOW
Hi-Z STATE
234
t
6
t
5
t
4
t
7
t
8
236012 F10
t
3
9101112
B11
(MSB)
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
BY TAKING CONV LOW, THE DEVICE POWERS UP
AND ACQUIRES AN INPUT ACCURATELY AFTER t
ACQ
SLEEP MODE
t
CONV
CONV
SCK
SDO
t
1
t
ACQ
t
THROUGHPUT
t
2
B10 B9 B3 B2 B1 B0*
Figure 10. LTC2360/LTC2361/LTC2362 Serial Interface Timing Diagram
