LTC2360/LTC2361/LTC2362
5
236012fa
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at T
A
= 25°C. (Note 4)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When pins A
IN
and V
REF
are taken below GND or above V
DD
,
they will be clamped by internal diodes. These products can handle input
currents greater than 100mA below GND or above V
DD
without latch-up.
Note 4: V
DD
= OV
DD
= V
REF
= 2.35V to 3.6V, f
SMPL
= f
SMPL(MAX)
and
f
SCK
= f
SCK(MAX)
unless otherwise specifi ed.
Note 5: Integral linearity is defi ned as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
SYMBOL PARAMETER CONDITIONS
LTC2360 LTC2361 LTC2362
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
f
SMPL(MAX)
Maximum Sampling Frequency (Notes 8, 9)
l
100 250 500 kHz
f
SCK
Shift Clock Frequency (Notes 8, 9)
l
10 25 50 MHz
t
SCK
Shift Clock Period
l
100 40 20 ns
t
THROUGHPUT
Minimum Throughput Time, t
ACQ
+ t
CONV
l
10 4 2 µs
t
ACQ
Acquisition Time
l
2 1 0.5 µs
t
CONV
Conversion Time
l
8 3 1.5 µs
t
1
Minimum Positive CONV Pulse Width (Note 8)
l
8 3 1.5 µs
t
2
SCK↑ Setup Time After CONV↓
(Note 8)
l
16 16 16 ns
t
3
SDO Enabled Time After CONV↓
(Notes 8, 9)
l
16 16 16 ns
t
4
SDO Data Valid Access Time After SCK↓
(Notes 8, 9, 10)
l
888ns
t
5
SCK Low Time (Note 11)
l
40% 40% 40% t
SCK
t
6
SCK High Time (Note 11)
l
40% 40% 40% t
SCK
t
7
SDO Data Valid Hold Time After SCK↓
(Notes 8, 9, 10)
l
444 ns
t
8
SDO Into Hi-Z State Time After CONV↑
(Notes 8, 9) 6 6 6 ns
Note 6: Linearity, offset and gain specifi cations apply for a single-ended
A
IN
input with respect to GND.
Note 7: Typical RMS noise at code transitions.
Note 8: Guaranteed by characterization. All input signals are specifi ed with
t
r
= t
f
= 2ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6V.
Note 9: All timing specifi cations given are with a 10pF capacitance load.
With a capacitance load greater than this value, a digital buffer or latch
must be used.
Note 10: The time required for the output to cross the V
IH
or V
IL
voltage.
Note 11: Guaranteed by design, not subject to test.
Note 12: High temperatures degrade operating lifetimes. Operating lifetime
is derated at temperatures greater than 105°C.
