LTC2360/LTC2361/LTC2362
9
236012fa
PIN FUNCTIONS
S6 Package
V
DD
(Pin 1): Positive Supply. The V
DD
range is 2.35V to
3.6V. V
DD
also defi nes the input span of the ADC, 0V to
V
DD
. Bypass to GND and to a solid ground plane with a
2.2F ceramic capacitor (or 2.2F tantalum in parallel
with 0.1F ceramic).
GND (Pin 2): Ground. The GND pin must be tied directly
to a solid ground plane.
A
IN
(Pin 3): Analog Input. A
IN
is a single-ended input with
respect to GND with a range from 0V to V
DD
.
SCK (Pin 4): Shift Clock Input. The SCK serial clock syn-
chronizes the serial data transfer. SDO data transitions on
the falling edge of SCK.
SDO (Pin 5): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB fi rst. The data stream consists of 12 bits
of conversion data followed by trailing zeros.
CONV (Pin 6): Convert Input. This active high signal starts
a conversion on the rising edge. The device automatically
powers down after conversion. A logic low on this input
enables the SDO pin, allowing the data to be shifted out.
TS8 Package
V
DD
(Pin 1): Positive Supply. The V
DD
range is 2.35V to
3.6V. Bypass to GND and to a solid ground plane with a
2.2F ceramic capacitor (or 2.2F tantalum in parallel
with 0.1F ceramic).
V
REF
(Pin 2): Reference Input. V
REF
defi nes the input
span of the ADC, 0V to V
REF
. The V
REF
range is 1.4V to
V
DD
. Bypass to GND and to a solid ground plane with a
2.2F ceramic capacitor (or 2.2F tantalum in parallel
with 0.1F ceramic).
GND (Pin 3): Ground. The GND pin must be tied directly
to a solid ground plane.
A
IN
(Pin 4): Analog Input. A
IN
is a single-ended input with
respect to GND with a range from 0V to V
REF
.
OV
DD
(Pin 5): Output Driver Supply for SDO. The OV
DD
range is 1V to V
DD
. Bypass to GND and to a solid ground
plane with a 2.2F ceramic capacitor (or 2.2F tantalum in
parallel with 0.1F ceramic). OV
DD
can be driven separately
from V
DD
and OV
DD
can be higher than V
DD
.
SDO (Pin 6): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB fi rst. The data stream consists of 12 bits
of conversion data followed by trailing zeros.
SCK (Pin 7): Shift Clock Input. The SCK serial clock syn-
chronizes the serial data transfer. SDO data transitions on
the falling edge of SCK.
CONV (Pin 8): Convert Input. This active high signal starts
a conversion on the rising edge. The device automatically
powers down after conversion. A logic low on this input
enables the SDO pin, allowing the data to be shifted out.
