NCV7361A
http://onsemi.com
12
Normal Mode Sleep Mode
Normal Mode
POR
UVR
POR
UVR
EN = H/L
Figure 16. Operating of Power On and Undervoltage RESET
V
SUP
V
SUVR_OFF
V
SUVR_ON
V
OUT
Mode
Control
Input
(internal*)
*reference Figure 1 Block Diagram
Switching into sleep mode can be done independently
from the current transceiver state. That means if the
transmitter is in dominant state this state will be cancelled
and it will be switched to recessive state.
POR−state
This is the power−on−reset state of the NCV7361A,
while V
SUP
< V
SUVR_OFF
. If the prior state was sleep mode,
the NCV7361A switches via the Ini−state to normal mode.
Ini−state
This is an intermediate state, which will pass through
after switch−on of V
SUP
or V
OUT
. The NCV7361A remains
in this state if V
OUT
is below V
RES
(Reset Output = L) and
V
SUP
> V
SUVR_ON
.
Thermal Shutdown
If the junction temperature T
J
is higher than T
JSHD
(>155°C), the NCV7361A will be switched into the
thermal shutdown mode. The behavior within this mode is
comparable with the sleep mode except for LIN transceiver
operating. The transceiver is completely disabled, no
wake−up functionality is available.
If T
J
falls below the thermal recovery temperature T
JREC
(typical 140°C) the NCV7361A will be recover to the
previous state (normal or sleep).
Initialization
Initialization is started if the power supply is switched on
as well as every rising edge on of the NCV7361A via the
EN pin.
V
SUP
− Power On
If V
SUP
is switched on the NCV7361A starts to normal
mode via the POR− and Ini−state. A combination of
dynamic POR and undervoltage reset circuitry generates a
POR signal, which switches the NCV7361A into normal
mode. This power on behavior is independent from the
status of the EN pin.
Power−on−Reset and undervoltage reset operates
independent from each other, which secures the
independence from the rise time of V
SUP
. During fast V
SUP
edges the Power−on−Reset will be active. If the increasing
of V
SUP
is very slow (> 1 ms/V) the undervoltage reset unit
initializes the voltage regulator if V
SUP
> V
SUVR_OFF
(typical 3.5 V).
The effects of both POR circuits at different V
SUP
slopes
as shown in Figure 16.
After POR the voltage regulator starts and V
OUT
will be
output. If V
OUT
> V
MRes
the bus interface will be activated.
If the V
OUT
voltage level is higher than V
RES
, the reset time
t
Res
= 100 ms is started. After t
Res
the RESET output
switches from low to high (Figure 16).
Start of Linear Regulator via Wake−Up
The initialization is only being done for the V
OUT
circuitry parts. This procedure begins with leaving the
master reset state (V
OUT
> V
MRes
) and runs in the same
manner as the V
SUP
− Power−On.
Wake−Up
If the regulator is put into sleep mode it can be
“waked−up” with the BUS interface. Every pulse on the
BUS (high pulse or low pulse) with a pulse width of
minimum 60 ms switches on the regulator.
After the BUS has “waked−up” the regulator, it can only
be switched off with a high level followed by a low level
on the EN pin.
V
SUP
Undervoltage Reset
The undervoltage detection unit inhibit an undefined
behavior of the NCV7361A under low voltage condition.
If V
SUP
drops below V
SUVR_ON
(typical 3 V) the
undervoltage detection becomes active and the IC will be
switched to POR state. The following increasing of V
SUP
above V
SUVR_OFF
(typical 3.5 V) cancels this POR state
and the voltage regulator starts with the initialization
sequence.
V
SUP
Undervoltage in Normal Mode
Supply Voltages below V
SUVR_OFF
do not influence the
voltage regulator. The output voltage V
OUT
follows V
SUP
.
