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NCV7361ADG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
NCV7361A
http://onsemi.com
13
V
SUP
Undervoltage in Sleep Mode
No exit from the sleep mode will take place if the V
SUP
voltage drops down to V
SUVR_ON
(typical 3.0 V). The
undervoltage reset becomes active (POR−state). As a result
of this operating, the sleep mode is left to the normal mode.
If V
SUP
rises again above V
SUVR_OFF
(typical 3.5 V), the
IC initializes the voltage regulator and continues to work
with the normal mode.
The undervoltage reset unit secures stable operating in
the undervoltage range of V
SUP
down to GND level. The
dynamic Power−On−Reset secures a defined internal state
independent from the duration of the V
SUP
drop, which
secures a stable restart.
Overtemperature Shutdown
If the junction temperature is 155°C < T
J
< 170°C the
overtemperature recognition will be activated and the
regulator voltage will be switched off. The V
OUT
voltage
drops down, the reset state is entered and the
bus−transceiver is switched off (recessive state).
After T
J
falls below 140°C the NCV7361A will be
initialized again (Figure 17) independently from the
voltage levels on EN and BUS. Within the thermal
shutdown mode the transceiver can not be switched to the
normal mode neither with local nor with remote wake−up.
The operation of the NCV7361A is possible between
T
Amax
(125°C) and the switch−off temperature, but small
parameter differences can appear.
After overtemperature switch−off the IC behaves as
described in Figure 17.
LIN BUS Transceiver
The NCV7361A is a bidirectional bus interface device
for data transfer between the LIN bus and the LIN protocol
controller.
The transceiver consists of a pnp−driver (1.2 V @
40 mA) with slew rate control, wave shaping and current
limit, and a high voltage receiver/comparator followed by
a filter circuit.
Transmit Mode
During transmission the data at the TxD pin will be
transferred to the BUS driver for generating a BUS signal.
To minimize the electromagnetic emission of the bus line,
the BUS driver has integrated slew rate control and wave
shaping circuitry.
Transmitting will be interrupted in the following cases:
• Sleep Mode
• Thermal Shutdown Active
• Master Reset (V
OUT
< 3.15 V)
The recessive BUS level is generated from the integrated
30 k pullup resistor in series with a diode This diode
prevents reverse current on V
BUS
when V
BUS
> V
SUP
.
No additional termination resistor is necessary to use the
NCV7361A in LIN slave nodes. If this IC is used for LIN
master nodes, it is necessary to terminate the bus pin with
an external 1.0 kW resistor in series with a diode to V
BAT
.
Receive Mode
The data signal from the BUS pin will be transferred
continuously to the pin RxD. Short spikes on the bus are
suppressed by the internal filter circuit (t = 2.8 ms).
Figure 17. RESET Behavior
t
rr
t
Res
V
SUP
RESET
V
RES
V
OUT
t
Res
T>T
J
T<T
J
t<t
rr
t
Res
t<t
rr
t
Res
Initialization Thermal
shutdown
Spike V
SUP
Low voltage
V
SUP
Current limitation
active
Spike V
CC
NCV7361A
http://onsemi.com
14
Figure 18. Receive Mode Impulse Diagram
60%
t < t
deb_BUS
V
SUP
RxD
40%
BUS
50%
V
thr_max
V
thr_min
V
thr_hys
V
thr_cnt
t < t
deb_BUS
The receive threshold values V
thr_max
and V
thr_min
are
symmetrical to 0.5*V
SUP
with a hysteresis of 0.135*V
SUP
.
The LIN specific receive threshold is between 0.4*V
SUP
and 0.6 * V
SUP
.
Data Rate
The NCV7361A is a constant slew rate transceiver. The
bus driver works with a fixed slew rate range of 1.0 V/ms
v DV/DT v 2.5 V/m s. This principle provides good
symmetry of the slope times between recessive to dominant
and dominant to recessive slopes within the LIN bus load
range (C
BUS
, R
term
).
The NCV7361A guarantees data rates up to 20 kb within
the complete bus load range under worst case conditions.
The constant slew rate principle holds appropriate voltage
levels and can operate within the LIN Protocol
Specification for RC oscillator systems with a matching
tolerance up to "2% between 2 nodes.
TxD Input
The 5.0 V input TxD directly controls the BUS level:
TxD = low → BUS = low (dominant level)
TxD = high → BUS = high (recessive level)
The TxD pin has an internal pullup resistor connected to
V
OUT
. This guarantees that an open TxD pin generates a
recessive BUS level.
Figure 19. TxD Input Circuitry
RC Filter
(10 ns)
Typ.
15 k
NCV7361AMCU
TxD
R
PU_TxD
I
PU_TxD
V
CC
V
OUT
NCV7361A
http://onsemi.com
15
RxD Output
The received BUS signal will be output to the 5.0 V RxD
pin:
BUS < V
thr_cnt
– 0.5 * V
thr_hys
→ RxD = low
BUS > V
thr_cnt
+ 0.5 * V
thr_hys
→ RxD = high
This output is a push−pull driver between V
OUT
and
GND with an output current capability of 1.0 mA.
Figure 20. RxD Output Circuitry
NCV7361A MCU
RxD
V
OUT
Linear Regulator
The NCV7361A has an integrated low dropout linear
regulator with a P−Channel MOSFET output driver whose
output is 5.0 V "2% at v50 mA and 5.5 V v V
SUP
v
18 V. Figure 21 shows typical current limit based on the
output voltage.
Figure 21. Characteristic of Current Limit
vs. Output Voltage
05632
V
OUT
(V)
IV
OUT
(mA)
120
40
0
14
80
100
20
60
RESET
RESET switches from low to high if V
SUP
is switched on
and V
OUT
> V
RES
for t
Res
.
If V
OUT
drops below V
RES
, the RESET output goes from
high to low after t
rr
. Short transients will be filtered.
The RESET output driver is driven from V
OUT
to
guarantee proper operation.
Figure 22. Output Current of Reset Output vs.
V
OUT
Voltage
16
14
12
10
8
6
4
2
0
0 0.5 1.0 1.5 2.0 3.0 3.5 4.0 4.52.5
V
OUT
(V)
lol_RESET (mA)
Initialization
The initialization is started if V
SUP
is switched on. This
is independent of the EN pin.
V
SUP
Power ON
The NCV7361A starts in the normal mode when V
SUP
is
applied [>3.15 V (typical)]. The internal circuitry on V
OUT
as well as the internal regulator starts the initialization with
power−on−reset. The voltage regulator is switched on.
If V
OUT
> V
POR
the bus−interface will be activated.
If V
OUT
is higher than V
Res
, the reset time t
Res
= 100 ms
is started. After t
Res
the RESET output switches from low
to high (Figure 22).
The initialization procedure at power on is started
independent from the EN state. The regulator can only be
turned off with a high level followed by a low level on the
EN pin.
Mode Input EN
The NCV7361A is switched into the sleep mode when
EN goes from high to low. The normal mode will be kept
as long as EN = high.
The regulator can be turned off by switching EN high to
low independent of the state of the bus−transceiver.
The EN input is internally pulled down to guarantee a
low with no connection. In the high state, the pulldown
current will be switched off to reduce the quiescent current.
The maximum input voltage is V
SUP
. The threshold is
typical 2.1 V and therefore CMOS levels can be used as
input signals. Figure 23 shows the internal circuitry of the
EN pin.
The EN input is internally pulled down to secure that if
this pin is not connected a low level will be generated. It
will be used two different pull down current sources for
high and low level to minimize the sleep mode current.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

NCV7361ADG

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Buy NCV7361ADG
Manufacturer:
ON Semiconductor
Description:
LDO Voltage Regulators ANA 10mA PLUS LIN
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