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MICRF505LYML-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43
Micrel MICRF505BML/YML
August 2006 19
M9999-092904
+1 408-944-0800
Low Dropout Regulator
The MICRF505LBML/YML has an internal voltage
regulator powering the MICRF505 device. This LDO
is equipped with a logic-compatible enable pin and
can be put into a zero-off-mode current state,
drawing no current when disabled. The LDO is a
µCap design operating with very small ceramic
output capacitors for stability.
Enable/Shutdown
The internal LDO comes with an active-high enable
pin that allows the regulator to be disabled. Forcing
the enable pin low disables the regulator and sends
it into a “zero” off-mode-current
state. In this state, current consumed by the
regulator goes nearly to zero. Forcing the enable pin
high enables the output voltage. The active-high
enable pin uses CMOS technology and the enable
pin cannot be left floating; a floating enable pin may
cause an indeterminate state on the output.
Input Capacitor
The LDO require a well-bypassed input supply for
optimal performance. A 1
µF capacitor is required
from the input to ground to provide stability. Low-
ESR ceramic capacitors provide optimal
performance at a minimum of space. Additional high
frequency capacitors, such as small-valued NPO
dielectric-type capacitors, help filter out high-
frequency noise and are good practice in any RF-
based circuit.
Output Capacitor
The LDO require an output capacitor of 1µF or
greater to maintain stability. The design is optimized
for use with low-ESR ceramic chip capacitors. High
ESR capacitors may cause high frequency
oscillation. The output capacitor can be increased,
but performance has been optimized for a 1
µF
ceramic output capacitor and does not improve
significantly with larger capacitance. X7R/X5R
dielectric-type ceramic capacitors are recommended
because of their temperature performance. X7R-
type capacitors change capacitance by 15% over
their operating temperature range and are the most
stable type of ceramic capacitors. Z5U and Y5V
dielectric capacitors change value by as much as
50% and 60%, respectively, over their operating
temperature ranges. To use a ceramic chip capacitor
with Y5V dielectric, the value must be much higher
than an X7R ceramic capacitor to ensure the same
minimum capacitance over the equivalent operating
temperature range.
Bypass Capacitor
A capacitor can be placed from the noise bypass pin
to ground to reduce output voltage noise. The
capacitor bypasses the internal reference. A 0.1
µF
capacitor is recommended for applications that
require low-noise outputs. The bypass capacitor can
be increased, further reducing noise and improving
PSRR. Turn-on time increases slightly with respect
to bypass capacitance. A unique, quick-start circuit
allows the LDO to drive a large capacitor on the
bypass pin without significantly slowing turn-on time.
Refer to the Typical Characteristics section for
performance with different bypass capacitors.
Micrel MICRF505BML/YML
August 2006 20
M9999-092904
+1 408-944-0800
Transceiver Sync/Non-Synchronous Mode
A6..A0 D7 D6 D5 D4 D3 D2 D1 D0
0000000 LNA_by PA2 PA1 PA0 Sync_en Mode1 Mode0 Load_en
0000110 - Mod_clkS2 Mod_clkS1 Mod_clkS0
BitSync_clk
S2
BitSync_clk
S1
BitSync_clk
S0
BitRate_clkS
2
0000111
BitRate_clkS
1
BitRate_clkS
0
RefClk_K5 RefClk_K4 RefClk_K3 RefClk_K2 RefClk_K1 RefClk_K0
Sync_en State Comments
0
Rx: Bit
synchronization off
Transparent reception of data
0 Tx: DataClk pin off Transparent transmission of data
1
Rx: Bit
synchronization on
Bit-clock is generated by transceiver
1
Tx: DATACLK pin
on
Bit-clock is generated by transceiver
When Sync_en = 1, it will enable the bit
synchronizer in receive mode. The bit synchronizer
clock needs to be programmed, see chapter Bit
synchronizer. The synchronized clock will be set out
on pit DATACLK.
In transmit mode, when Sync_en = 1, the clock
signal on pin DATACLK is a programmed bit rate
clock. Now the transceiver controls the actual data
rate. The data to be transmitted will be sampled on
rising edge of DATACLK. The micro controller can
therefore use the negative edge to change the data
to be transmitted. The clock used for this purpose,
BITRATE_CLK, is programmed in the same way as
the modulator clock and the bit synchronizer clock:
)-(7
XCO
KBITRATE_CL
2Refclk_K
f
f
kSBitRate_cl
×
=
where:
f
BITRATE_CLK
: The clock frequency used to
control the bit rate, should be equal to the bit
rate (bit rate of 20 kbit/sec requires a clock
requency of 20kHz)
f
XCO
: Crystal oscillator frequency
Refclk_K: 6 bit divider, values between 1
and 63
BitRate_clkS: Bit rate setting, values
between 0 and 6
Data Interface
The MICRF505 interface can be divided in to two
separate interfaces, a “programming interface” and a
“Data interface”. The “programming interface” has a
three wire serial programmable interface and is
described in chapter Programming.
The “data interface” can be programmed to sync-
/non-synchronous mode. In synchronous mode the
MICRF505 is defined as “Master” and provides a
data clock that allows users to utilize low cost micro
controller reference frequency.
The data interface is defined in such a way that all
user actions should take place on falling edge and is
illustrated Figure 9 and 10. The two figures illustrate
the relationship between DATACLK and DATAIXO
in receive mode and transmit mode.
MICRF505 will present data on rising edge and the
“USER” sample data on falling edge in receive
mode.
DATAIXO
DATACLK
Figure 10. Data interface in Receive Mode
The User presents data on falling edge and
MICRF505 samples on rising edge in transmit mode.
DATAIXO
DATACLK
Figure 11. Data interface in Transmit Mode
When entering transmit mode it is important to keep
DATAIXO in tri-state from the time Tx-mode is
entered until user starts sending data. The data is
provided directly to the modulation circuit and
violation of this may/will cause abnormal behavior.
Depending upon the chosen FSK modulation, some
sort of encoding might be needed. The different
modulation types and encoding is described in
chapter Frequency modulation.
Micrel MICRF505BML/YML
August 2006 21
M9999-092904
+1 408-944-0800
Receiver
The receiver is a zero intermediate frequency (IF)
type in order to make channel filtering possible with
low-power integrated low-pass filters. The receiver
consists of a low noise amplifier (LNA) that drives a
quadrature mixer pair. The mixer outputs feed two
identical signal channels in phase quadrature. Each
channel include a pre-amplifier, a third order Sallen-
Key RC lowpass filter from strong adjacent channel
signals and finally a limiter. The main channel filter is
a switched-capacitor implementation of a six-pole
elliptic lowpass filte. The elliptic filter minimizes the
total capacitance required for a given selectivity and
dynamic range. The cut-off frequency of the Sallen-
Key RC filter can be programmed to four different
frequencies: 100kHz, 150kHz, 230kHz and 340kHz.
The demodulator demodulates the I and Q channel
outputs and produces a digital data output. If detects
the relative phase of the I and Q channel signal. If
the I channel signal lags the Q channel, the FSK
tone frequency lies above the LO frequency (data
‘1’). If the I channel leads the Q channel, the FSK
tone lies below the LO frequency (data ‘0’). The
output of the receiver is available on the DataIXO
pin. A RSSI circuit (receive signal strength indicator)
indicates the received signal level.
Front End
A6..A0 D7 D6 D5 D4 D3 D2 D1 D0
0000000 LNA_by PA2 PA1 PA0 Sync_en Mode1 Mode0 Load_en
A low noise amplifier in RF receivers is used to
boost the incoming signal prior to the frequency
conversion process. This is important in order to
prevent mixer noise from dominating the overall
front-end noise performance. The LNA is a two-
stage amplifier and has a nominal gain of
approximately 23dB at 900MHz. The front end has a
gain of about 33dB to 35dB. The gain varies by 1-
1.5dB over a 2.0V to 2.5V variation in power supply.
The LNA can be bypassed by setting bit LNA_by to
‘1’. This can be useful for very strong input signal
levels. The front-end gain with the LNA bypassed is
about 9-10dB. The mixers have a going of about
10dB at 915MHz. The differential outputs of the
mixers can be made available at pins IchOut and
QchOut. The output impedance of each mixer is
about 8k
Ω.
The input impedance is close to 50
Ω as shown in
Figure 12, giving an input reflection of about -20dB.
The receiver does not require any matching network
to optimize the gain. However, a matching network is
recommended for harmonic suppression in Tx and
for improved selectivity in Rx.
Figure 12. LNA Input Impedance
Sallen-Key Filters
A6..A0 D7 D6 D5 D4 D3 D2 D1 D0
0000001 Modulation1 Modulation0 ‘0’ ‘0’ RSSI_en LD_en PF_FC1 PF_FC0
Each channel includes a pre-amplifier and a prefilter,
which is a three-pole Sallen-Key lowpass filter. It
protects the following switched-capacitor filter from
strong adjacent channel signals, and it also works as
an anti-aliasing filter. The preamplifier has a gain of
22-23dB. The maximum output voltage swing is
about 1.4Vpp for a 2.25V power supply. In addition,
the IF amplifier also performs offset cancellation.
Gain varies by less than 0.5dB over a 2.0 – 2.5V
variation in power supply. The third order Sallen-Key
lowpass filter is programmable to four different cut-
off frequencies according to the table below:
PF_FC1 PF_FC0 Cut-off Freq. (kHz)
0 0 100
0 1 150
1 0 230
1 1 340
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43

MICRF505LYML-TR

Mfr. #:
Buy MICRF505LYML-TR
Manufacturer:
Microchip Technology / Micrel
Description:
RF Transceiver
Lifecycle:
New from this manufacturer.
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