MICRF505LYML-TR Datasheet MICRF505LYML-TR | P25-P27

Micrel MICRF505

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Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

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Transmitter

Power Amplifier

A6..A0 D7 D6 D5 D4 D3 D2 D1 D0

0000000 LNA_by PA2 PA1 PA0 Sync_en Mode1 Mode0 Load_en

0000001 Modulation1 Modulation0 ‘0’ ‘0’ RSSI_en LD_en PF_FC1 PF_FC0

0000010 CP_HI SC_by ‘0’ PA_By OUTS3 OUTS2 OUTS1 OUTS0

The maximum output power is approximately 10dBm

for a 50

Ω load. For maximum output power the load

seen by the PA must be resistive. Higher output

power can be obtained by decreasing the load

impedance. However, this will be in conflict with

obtaining impedance match in the LNA. The output

power is programmable in seven steps, with

approximately 3dB between each step. This is

controlled by bits PA2 – PA0.

The power amplifier can be turned off by setting PA2

– PA0 = 0.

For all other combinations the PA is on and has

maximum power when PA2 – PA0 = 1.

The PA will be bypassed if PA_by=1. Output power

will drop ~22dB. It is still possible to control the

power by PA2 – PA0.

The output power varies about 3dB over power

supply 2.0V to 2.5V and about 2dB over temperature

-40˚C to +85˚C. The 2

and 3

harmonic of the PA

are as follows:

harmonic: <-16dBm

harmonic: <-8dBm

To reduce the emission of harmonics, an LC filter

can be added between the ANT pin and the antenna

as shown in Figure 15.

ANT

50ohm line 50ohm line

3p3

2p2

8n7

8p2

Figure 15. LC Filter

This filter is designed for the 915MHz band with 50Ω

terminations. The component values may have to be

tuned to compensate for the layout parasitics. This

filter may also increase the receiver selectivity.

Frequency Modulation

A6..A0 D7 D6 D5 D4 D3 D2 D1 D0

0000001 Modulation1 Modulation0 ‘0’ ‘0’ RSSI_en LD_en PF_FC1 PF_FC0

Modulation1 Modulation0 Modulation Type

0 0 Closed loop modulation

using modulator

0 1 Not in use

1 0 FSK applied using two

sets of dividers

1 1 Not in use

Table 11. Modulation Bit Setting

When Modulation1 and Modulation0 is 00, the

modulator needs to be programmed properly, see

“Modulator” section. The modulation signal will now

be applied directly on the phase locked VCO. It is

therefore important that the PLL bandwidth is not too

high, as this will remove the modulation. See “PLL

Filter” section on how to calculate the PLL

components. When using the modulator the

modulation signal is applied to the VCO and

therefore some sort of encoding is needed.

The level of encoding is determined by the PLL loop

filter bandwidth and data rate. Two of the most

common encoding techniques are Manchester

encoding and 3B4B. Other encoding schemes may

also be used.

Manchester encoding is when one bit is encoded in

to a two-bit word and is shown in Table 10. When

using Manchester encoding the maximum overhead

is 100%. When selecting PLL loop filter it is

important to note that the min baud rate is equal to:

baud_min

baud /s

baud_min

: The minimum frequency of the baud

rate [Hz]

baud/s: Elements per second (encoded data)

Micrel MICRF505BML/YML

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Data Word

“0” “10”

“1” “01”

Table 12. Manchester Encoding

Another much more efficient encoding type is 3B4B

where three data bits are encoded into a four-bit

word. The reason for encoding is to minimize the DC

component in the modulated data. To have minimum

DC component each four bit word should include

two elements of “1” and two elements of “0”.

Following this guidance only 6 out of 8 word

complies and two encoded words needs special

precaution. Whenever 000 and 111 data appear, the

user must set/clear a flag that indicate if last

encoded word was “Word A” and select the

respective encoded word shown in Table 11.

Data Word A Word B

000 1011 0100

001 1100

010 0011

011 1010

100 0101

101 1001

110 0110

111 1101 0010

Table 13. 3B4B Encoding

When Modulation1 Modulation0 is 10, two sets of

divider values need to be programmed. The formula

for calculating the M, N and A values is given in

chapter Frequency synthesizer. The divider values

stored in the M0-, N0-, and A0- registers will be used

when transmitting a ‘0’ and the M1-, N1-, and A1-

registers will be used to transmit a ‘1’. The difference

between the two carrier frequencies corresponds to

the double sided frequency modulation. Opposite

from the modulation with the modulator, the PLL

shall now lock on a new frequency for every change

in the transmitted data. The PLL bandwidth therefore

needs to be relatively high, higher bit rate requires a

higher PLL bandwidth and vice versa. The data to

be transmitted shall be applied to pin DataIXO (see

chapter Transceiver sync-/non-synchronous mode

on how to use the pin DataClk). The DataIXO pin is

set as input in transmit mode and output in receive

mode. When set as input, a weak voltage divider will

set the level to Vdd/2, when it is not pulled up or

down by the controller. When using the modulator, it

is important that the DataIXO is kept tristated until

the transmission shall begin (when PLL is in lock

and the PA is turned on). When Data IXO is

tristated, the PLL will lock on the LO frequency

(used in receive mode). When DataIXO is set either

high or low, the RF frequency will be shifted up or

down, centered around the LO-frequency. This is

only important when using the modulator, for the

other modulation method, if DATAIXO is tristated,

the M0-, N0- and A0-registers will be used.

Data bits Encoded words Comments

000 000 000 000 000 1011 0100 1011 0100 1011 A Flag indicates if “Word A” has been used

111 111 010 110 000 1101 0010 0011 0110 1011 A Flag indicates if “Word A” has been used

Table 14. Example of 3B4B encoding

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Modulator

A6..A0 D7 D6 D5 D4 D3 D2 D1 D0

0000100 Mod_F2 Mod_F1 Mod_F0 Mod_I4 Mod_I3 Mod_I2 Mod_I1 Mod_I0

0000101 - - ‘0’ ‘1’ Mod_A3 Mod_A2 Mod_A1 Mod_A0

0000110 - Mod_clkS2 Mod_clkS1 Mod_clkS0 BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2

0000111 BitRate_clkS1 BitRate_clkS0 RefClk_K5 RefClk_K4 RefClk_K3 RefClk_K2 RefClk_K1 RefClk_K0

The modulator will create a waveform with

programmable amplitude and frequency. This

waveform is fed into a modulation varactor in the

VCO, which will create the desired frequency

modulation. The frequency spectrum can be

narrowed by increasing the rise-and fall times of the

waveform.

The modulator waveform is created by charging and

discharging a capacitor. A modulator clock controls

the timing, as shown in Figure19. For every rise-and

fall edge, 4 clock periods are being used. The

charging current during these 4 clock periods are not

equal, this is to reduce the high frequency

components in the waveform, which in turn will

narrow the frequency spectrum.

The frequency deviation can be set in three different

ways, as will be explained below. A formula for

setting the desired deviation is given at the end of

this chapter.

odulator Clock

odulator Waveform

Figure 19. Modulator Waveform and Clock

Modulator Clock

The modulator clock frequency is set by:

)(7

XCO

MOD_CLK

2Refclk_K

Mod_clkS−

where f

MOD_CLK

is the modulator clock shown in

Figure 19, f

XCO

is the crystal oscillator frequency

Refclk_K is a 6 bit number and Mod_clkS is a 3 bit

number. Mod_clkS can be set to a value between 0

and 7. The modulator clock frequency should be set

according to the bit rate and shaping.

Mod_clka

Mod_clkb

od_clkb > Mod_clka

Figure 20. Two Different Modulator Clock Setting

A f

MOD_CLK

of 8 times the bit rate (as in Figure 20)

corresponds to a signal filtered in a Gaussian filter

with a Bandwidth Period product (BT) of 1. When BT

is increased, the waveform will be less filtered.

Minimum BT is 1 (f

MOD_CLK

is 8 times the bitrate).

Figure 20 shows two waveforms with BT=1 and

BT=2, i.e. the f

MOD_CLK

is 8 and 16 times higher than

the bit rate. When changing the BT factor, the

charge-and discharge times will also be changed,

and therefore the frequency deviation, as shown in

Figure 19.

Modulator Current

The current used during the rise- and fall times can

be programmed with the Mod_I4..Mod_I0 bit, the

last one being LSB. Figure 21 shows two waveforms

generated with two different currents, where

IbModIaMod __ > . Higher current will give a

higher frequency deviation and vice versa. The

effect of modulator clock and MOD_1 is illustrated

by:

MOD_CLK

DEVIATION

MOD_1

f ∝

To avoid saturation in the modulator it is important

not to exceed maximum Mod_I. Maximum Mod_I for

a given f

MOD_clk

is given by:

1-)1028INT(fMOD_I

-6

MOD_CLKMAX

×⋅=

where INT() returns the integer part of the argument.

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