MICRF505LYML-TR Datasheet MICRF505LYML-TR | P22-P24

Micrel MICRF505BML/YML

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Switched Capacitor Filter

A6..A0 D7 D6 D5 D4 D3 D2 D1 D0

0001000 ‘1’ ScClk_X2 ScClk5 ScClk4 ScClk3 ScClk2 ScClk1 ScClk0

The main channel filter is a switched-capacitor

implementation of a six-pole elliptic low pass filter.

The elliptic filter minimized the total capacitance

required for a given selectivity and dynamic range.

The cut-off frequency of the switched-capacitor filter

is adjustable by changing the clock frequency.

The clock frequency is designed to be 20 times the

cut-off frequency. The clock frequency is derived

from the reference crystal oscillator. A

programmable 6-bit divider divides the frequency of

the crystal oscillator. To generate the correct non-

overlapping clock-phases needed by the filter this

frequency is then divided by 4. The cut-off frequency

of the filter is given by:

fCUT =

XCO

40 ⋅ ScClk

CUT

: Filter cutoff frequency

XCO

: Crystal oscillator frequency

ScClk: Switched capacitor filter clock, bits

ScClk5-0

For instance, for a crystal frequency of 16MHz and if

the 6 bit divider divides the input frequency by 4 the

cut-off frequency of the SC filter is 16MHz/(40 x 4) =

100kHz. 1

order RC low pass filters are connected

to the output of the SC filter-to-filter the clock

frequency.

The lowest cutoff frequency in the pre- and the main

channel filter must be set so that the received signal

is passed with no attenuation, which is frequency

deviation plus modulation. If there are any frequency

offset between the transmitter and the receiver, this

must also be taken into consideration. A formula for

the receiver bandwidth can be summarized as

follows:

2 / Baudrate f f f DEVOFFSETBW +++=

where

: Needed receiver bandwidth, fcut above

should not be smaller than f

[Hz]

OFFSET

: Total frequency offset between

receiver and transmitter [Hz]

DEV

: Single-sided frequency deviation, see

chapter Modulator on how to calculate [Hz]

Baudrate: The baud rate given is bit/sec

RSSI

A6..A0 D7 D6 D5 D4 D3 D2 D1 D0

0000001 Modulation1 Modulation0 ‘0’ ‘0’ RSSI_en LD_en PF_FC1 PF_FC0

RSSI

33kohm, 1nF, 125kbps, BW=200kHz, Vdd=2.5V

0.6

0.8

1.2

1.4

1.6

1.8

2.2

-125 -115 -105 -95 -85 -75 -65 -55 -45 -35 -25

Pin [dBm]

RSSI [V]

Figure 13. RSSI Voltage

C10

1nF

33k

Pin 14

RSSI

Figure 14. RSSI Network

A Typical plot of the RSSI voltage as function of

input power is shown in Figure 13. The RSSI has a

dynamic range of about 50dB from about -110dBm

to -60dBm input power.

The RSSI can be used as a signal presence

indicator. When a RF signal is received, the RSSI

output increases. This could be used to wake up

circuitry that is normally in a sleep mode

configuration to conserve battery life.

Another application for which the RSSI could be

used is to determine if transmit power can be

reduced in a system. If the RSSI detects a strong

signal, if could tell the transmitter to reduce the

transmit power to reduce current consumption.

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FEE

A6..A0 D7 D6 D5 D4 D3 D2 D1 D0

0010101 - - - - FEEC_3 FEEC_2 FEEC_1 FEEC_0

0010110 FEE_7 FEE_6 FEE_5 FEE_4 FEE_3 FEE_2 FEE_1 FEE_0

The Frequency Error Estimator (FEE) uses

information from the demodulator to calculate the

frequency offset between it’s receive frequency and

the transmitter frequency. The output of the FEE can

be used to tune the XCO frequency, both for

production calibration and for compensation for

crystal temperature drift and aging.

The inputs to the FEE circuit are the up and down

pulses from the demodulator. Every time a ‘1’ is

updated, an UP-pulse is coming out of the

demodulator, and the same with the DN-pulse every

time the ‘0’ is updated. The expected number of

pulses for every received symbol is 2 times the

modulation index (

∆).

The FEE can operate in three different modes;

counting only UP-pulses, only DN-pulses or counting

UP+DN pulses. The number of received symbols to

be counted is either 8, 16, 32 or 64. This is set by

the FEEC_0…FEEC_3 control bit, as follows:

FEEC_1 FEEC_0 FEE Mode

0 0 Off

0 1 Counting UP pulses

1 0 Counting DN pulses

1 1 Counting UP and DN pulses. UP increments

the counter, DN decrements it.

FEEC_3 FEEC_2 No. of symbols used for the measurement

0 0 8

0 1 16

1 0 32

1 1 65

Table 10. FEEC Control Bit

The result of the measurement is the FEE value, this

can be read from register with address 0010110b.

Negative values are stored as a binary no between

0000000 and 1111111. To calculate the negative

value, a two’s complement of this value must be

performed. Only FEE modes where DN-pulses are

counted (10 and 11) will give a negative value.

When the FEE value has been read, the frequency

offset can be calculated as follows:

Mode UP: Foffset = R/(2P)x(FEE-

∆Fp)

Mode DN: Foffset = R/(2P)x(FEE+

∆Fp)

Mode UP+DN: Foffset = R/(4P)x(FEE)

where FEE is the value stored in the FEE register,

(Fp is the single sided frequency deviation, P is the

number of symbols/data bit counted and R is the

symbol/data rate. A positive Foffset means that the

received signal has a higher frequency than the

receiver frequency. To compensate for this, the

receivers XCO frequency should be increased (see

ANNEX A) on how to tune the XCO frequency based

on the FEE value).

It is recommended to use Mode UP+DN for two

reasons, you do not need to know the actual

frequency deviation and this mode gives the best

accuracy.

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Bit Synchronizer

A6..A0 D7 D6 D5 D4 D3 D2 D1 D0

0000110 - ModclkS2 ModclkS1 ModclkS0 BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2

0000111 BitRate_clkS1 BitRate_clkS0 RefClk_K5 RefClk_K4 RefClk_K3 RefClk_K2 RefClk_K1 RefClk_K0

A bit synchronizer can be enabled in receive mode

by selecting the synchronous mode (Sync_en=1).

The DataClk pin will output a clock with twice the

frequency of the bit rate (a bit rate of 20 kbit/sec

gives a DataClk of 20 kHz). A received symbol/bit on

DataIXO will be output on rising edge of DataClk.

The micro controller should therefore sample the

symbol/bit on falling edge of DataClk.

The bit synchronizer uses a clock which needs to be

programmed according to the bit rate. The clock

frequency should be 16 times the actual bit rate (a

bit rate of 20 kbit/sec needs a bit synchronizer clock

with frequency of 320 kHz). The clock frequency is

set by the following formula:

fBITSYNC_CLK =

XCO

Refclk_K × 2

(7-

BITSYNC_clkS

)

where

BITSYNC_CLK

: The bit synchronizer clock

frequency (16 times higher than the bit rate)

XCO

: Crystal oscillator frequency

Refclk_K: 6 bit divider, values between 1 and

BitSync_clkS: Bit synchronizer setting, values

between 0 and 7

Refclk_K is also used to derive the modulator clock

and the bit rate clock.

At the beginning of a received data package, the bit

synchronizer clock frequency is not synchronized to

the bit rate. When these two are maximum offset to

each other, it takes 22 bit/symbols before

synchronization is achieved.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P43

MICRF505LYML-TR

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RF Transceiver

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