PCA8575_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 21 March 2007 13 of 30
NXP Semiconductors
PCA8575
Remote 16-bit I/O expander for I
2
C-bus with interrupt
9.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 17. System configuration
002aaa966
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I
2
C-BUS
MULTIPLEXER
SLAVE
Fig 18. Acknowledgement on the I
2
C-bus
002aaa987
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from master
PCA8575_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 21 March 2007 14 of 30
NXP Semiconductors
PCA8575
Remote 16-bit I/O expander for I
2
C-bus with interrupt
10. Application design-in information
10.1 Bidirectional I/O expander applications
In the 8-bit I/O expander application shown in Figure 19, P00 and P01 are inputs, and P02
to P07 are outputs. When used in this configuration, during a write, the input (P00 and
P01) must be written as HIGH so the external devices fully control the input ports. The
desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P02 to
P07). During a read, the logic levels of the external devices driving the input ports (P00
and P01) and the previous written logic level to the output ports (P02 to P07) will be read.
The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of
the microprocessor. By sending an interrupt signal on this line, the remote I/O informs the
microprocessor that there is incoming data or a change of data on its ports without having
to communicate via the I
2
C-bus.
10.2 High current-drive load applications
The GPIO has a maximum sinking current of 25 mA per bit. In applications requiring
additional drive, two port pins in the same octal may be connected together to sink up to
50 mA current. Both bits must then always be turned on or off together. Up to 8 pins (one
octal) can be connected together to drive 200 mA.
Fig 19. Bidirectional I/O expander application
002aab812
V
DD
temperature sensor
battery status
control for latch
control for switch
control for audio
control for camera
control for MP3
P00
P01
P02
P03
P04
P05
P06
P07
V
DD
SDA
SCL
INT
AD0
AD1
AD2
CORE
PROCESSOR
V
DD
Fig 20. High current-drive load application
002aab813
V
DD
P00
P01
P02
P03
P04
P05
P06
P07
V
DD
SDA
SCL
INT
AD0
AD1
AD2
CORE
PROCESSOR
V
DD
LOAD
PCA8575_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 21 March 2007 15 of 30
NXP Semiconductors
PCA8575
Remote 16-bit I/O expander for I
2
C-bus with interrupt
10.3 Differences between the PCA8575 and the PCF8575
The PCA8575 is a drop in replacement for the PCF8575 and can used without electrical
or software modifications, but there is a difference in interrupt output release timing during
the read operation.
Write operations are identical. At the completion of each 8-bit write sequence the data is
stored in its associated 8-bit write register at ACK or NACK. The first byte goes to P0n
while the second goes to P1n. Subsequent writes without a STOP wrap around to P0n
then P1n again. Any write will update both read registers and clear interrupts.
Read operations are identical. Both devices update the byte register with the pin data as
each 8-bit read is initiated, the very first read after an address cycle corresponds to ports
P0n while the second (even byte) corresponds to P1n and subsequent reads without a
STOP wrap around to P0n then P1n again.
During read operations, the PCA8575 interrupt output will be cleared in a byte-wise
fashion as each byte is read. Reading the first byte will clear any interrupts associated
with the P0n pins. This first byte read operation will have no effect on interrupts associated
with changes of state on the P1n pins. Interrupts associated with the P1n pins will be
cleared when the second byte is read. Reading the second byte has no effect on
interrupts associated with the changes of state on the P0x pins. The PCF8575 interrupt
output will clear after reading both bytes of data regardless of whether data was changed
in the first byte or the second byte or both bytes.
11. Limiting values
[1] Total package (maximum) output current is 600 mA.
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +6 V
I
DD
supply current - ±100 mA
I
SS
ground supply current - ±600 mA
V
I
input voltage V
SS
0.5 5.5 V
I
I
input current - ±20 mA
I
O
output current - ±50
[1]
mA
P
tot
total power dissipation - 600 mW
P/out power dissipation per output - 200 mW
T
stg
storage temperature 65 +150 °C
T
amb
ambient temperature operating 40 +85 °C

PCA8575BQ,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC I/O EXPANDER I2C 16B 24DHVQFN
Lifecycle:
New from this manufacturer.
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