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LT3431IFE#TRPBF

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16
LT3431
sn3431 3431fs
APPLICATIO S I FOR ATIO
WUUU
Threshold voltage for lockout is about 2.38V. A 5.5µA bias
current flows
out
of the pin at this threshold. The internally
generated current is used to force a default high state on
the shutdown pin if the pin is left open. When low shut-
down current is not an issue, the error due to this current
can be minimized by making R
LO
10k or less. If shutdown
current is an issue, R
LO
can be raised to 100k, but the error
due to initial bias current and changes with temperature
should be considered.
Rk
R
RV V
VR A
LO
HI
LO IN
LO
=
()
=
−
()
−
()
10
238
238 55
to 100k 25k suggested
.
..µ
V
IN
= Minimum input voltage
Keep the connections from the resistors to the shutdown
pin short and make sure that interplane or surface capaci-
tance to the switching nodes are minimized. If high
resistor values are used, the shutdown pin should be
bypassed with a 1000pF capacitor to prevent coupling
problems from the switch node. If hysteresis is desired in
the undervoltage lockout point, a resistor R
FB
can be
added to the output node. Resistor values can be calcu-
lated from:
R
RV VV V
RA
RRV V
HI
LO IN OUT
LO
FB HI OUT
=
−+
()
+
[]
−
()
=
()( )
238 1
238 55
./
..
/
∆∆
∆
µ
25k suggested for R
LO
V
IN
= Input voltage at which switching stops as input
voltage descends to trip level
∆V = Hysteresis in input voltage level
Example: output voltage is 5V, switching is to stop if input
voltage drops below 12V and should not restart unless
input rises back to 13.5V. ∆V is therefore 1.5V and
V
IN
␣ =␣ 12V. Let R
LO
= 25k.
R
k
kA
k
k
Rk k
HI
FB
=
−+
()
+
[]
µ
()
=
()
=
=
()
=
25 12 238155 1 15
238 25 55
25 10 41
224
116
116 5 1 5 387
../ .
.– .
.
.
/.
SYNCHRONIZING
The SYNC input must pass from a logic level low, through
the maximum synchronization threshold with a duty cycle
between 10% and 90%. The input can be driven directly
from a logic level output. The synchronizing range is equal
to
initial
operating frequency up to 700kHz. This means
that
minimum
practical sync frequency is equal to the
worst-case
high
self-oscillating frequency (570kHz), not
the typical operating frequency of 500kHz. Caution should
be used when synchronizing above 662kHz because at
higher sync frequencies the amplitude of the internal slope
compensation used to prevent subharmonic switching is
–
+
–
+
2.38V
0.4V
GND
V
SW
LT3431
INPUT
R
FB
R
HI
3431 F04
OUTPUT
C1
L1
SHDN
STANDBY
IN
TOTAL
SHUTDOWN
5.5µA
R
LO
C2
+
Figure 4. Undervoltage Lockout
17
LT3431
sn3431 3431fs
APPLICATIO S I FOR ATIO
WUUU
reduced. This type of subharmonic switching only occurs
at input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
At power-up, when V
C
is being clamped by the FB pin (see
Figure 2, Q2), the sync function is disabled. This allows the
frequency foldback to operate in the shorted output con-
dition. During normal operation, switching frequency is
controlled by the internal oscillator until the FB pin reaches
0.6V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
to ground.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal elec-
trical, thermal and noise performance. For maximum
efficiency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. This is imple-
mented in the suggested layout of Figure 6. Shortening
this path will also reduce the parasitic trace inductance of
approximately 25nH/inch. At switch off, this parasitic in-
ductance produces a flyback spike across the LT3431
switch. When operating at higher currents and input volt-
ages, with poor layout, this spike can generate voltages
across the LT3431 that may exceed its absolute maximum
rating. A ground plane should always be used under the
switcher circuitry to prevent interplane coupling and over-
all noise.
GND GND1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHDN
SYNC
GND
BOOST
V
IN
V
IN
SW
SW
PLACE FEEDTHROUGH AROUND
GROUND PINS (4 CORNERS) FOR
GOOD THERMAL CONDUCTIVITY
LT3431
C3
C1
D1
C2
D2
3431 F06
C
C
R
C
C
F
L1
MINIMIZE LT3430
C3-D1 LOOP
V
IN
PINS 3 AND 4
ARE SHORTED TOGETHER.
SW PINS 2 AND 5 ARE ALSO
SHORTED TOGETHER (USING
AVAILABLE SPACE UNDERNEATH
THE DEVICE BETWEEN PINS AND
GND PLANE)
GND
GND
BIAS
FB
V
C
CONNECT TO
GROUND PLANE
KELVIN SENSE
V
OUT
KEEP FB AND V
C
COMPONENTS
AWAY FROM HIGH FREQUENCY,
HIGH CURRENT COMPONENTS
SOLDER THE EXPOSED PAD
TO THE ENTIRE COPPER
GROUND PLANE UNDERNEATH
THE DEVICE. NOTE: THE BOOST
AND BIAS COPPER TRACES ARE
ON A SEPARATE LAYER FROM
THE GROUND PLANE
GND
V
OUT
V
IN
GND1
2
3
4
5
6 BOOST
V
IN
V
IN
SW
SW
LT3431
R2
R1
CFB
Figure 6. Suggested Layout
3431 F05
5V
L1
V
IN
LT3431
D1C3 C1
HIGH
FREQUENCY
CIRCULATING
PATH
LOAD
Figure 5. High Speed Switching Path
18
LT3431
sn3431 3431fs
APPLICATIO S I FOR ATIO
WUUU
The V
C
and FB components should be kept as far away as
possible from the switch and boost nodes. The LT3431
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
Board layout also has a significant effect on thermal
resistance. Pins 1, 8, 9 and 16, GND, are a continuous
copper plate that runs under the LT3431 die. This is an
exposed pad and is the best thermal path for heat out of the
package. Soldering the exposed pad to the copper ground
plane under the device will reduce die temperature and
increase the power capability of the LT3431. Adding
multiple solder filled feedthroughs under and around the
four corner pins to the ground plane will also help. Similar
treatment to the catch diode and coil terminations will
reduce any additional heating effects.
PARASITIC RESONANCE
Resonance or “ringing” may sometimes be seen on the
switch node (see Figure 7). Very high frequency ringing
following switch rise time is caused by switch/diode/input
capacitor lead inductance and diode capacitance. Schot-
tky diodes have very high “Q” junction capacitance that
can ring for many cycles when excited at high frequency.
If total lead length for the input capacitor, diode and
switch path is 1 inch, the inductance will be approximately
25nH. At switch off, this will produce a spike across the
NPN output device in addition to the input voltage. At
higher currents this spike can be in the order of 10V to 20V
or higher with a poor layout, potentially exceeding the
abso
lute max switch voltage. The path around switch,
catch diode and input capacitor must be kept as short as
possible to ensure reliable operation. When looking at this,
a >100MHz oscilloscope must be used, and waveforms
should be observed on the leads of the package. This
switch off spike will also cause the SW node to go below
ground. The LT3431 has special circuitry inside which
mitigates this problem, but negative voltages over 0.8V
lasting longer than 10ns should be avoided. Note that
100MHz oscilloscopes are barely fast enough to see the
details of the falling edge overshoot in Figure 7.
A second, much lower frequency ringing is seen during
switch off time if load current is low enough to allow the
inductor current to fall to zero during part of the switch off
time (see Figure 8). Switch and diode capacitance reso-
nate with the inductor to form damped ringing at 1MHz to
10MHz. This ringing is not harmful to the regulator and it
has not been shown to contribute significantly to EMI. Any
attempt to damp it with a resistive snubber will degrade
efficiency.
50ns/DIV
3431 F07
2V/DIV
SW RISE SW FALL
Figure 7. Switch Node Resonance
THERMAL CALCULATIONS
Power dissipation in the LT3431 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
Figure 8. Discontinuous Mode Ringing
5V/DIV
0.2A/DIV
SWITCH NODE
VOLTAGE
INDUCTOR
CURRENT AT
I
OUT
= 0.1A
V
IN
= 12V 500ns/DIV 3431 F08
V
OUT
= 5V
L = 10µH
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LT3431IFE#TRPBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi V, 3A, 500kHz Buck Sw Reg
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