19
LT3431
sn3431 3431fs
Switch loss:
P
RI V
V
tIVf
SW
SW OUT OUT
IN
EFF OUT IN
=
()( )
+
()()()
2
12(/ )
Boost current loss:
P
VI
V
BOOST
OUT OUT
IN
=
()
2
36/
Quiescent current loss:
PV V
Q IN OUT
=
()
+
()
0 0015 0 003..
R
SW
= Switch resistance (0.15) hot
t
EFF
= Effective switch current/voltage overlap time
= (t
r
+ t
f
+ t
Ir
+ t
If
)
t
r
= (V
IN
/1.2)ns
t
f
= (V
IN
/1.1)ns
t
Ir
= t
If
= (I
OUT
/0.05)ns
f = Switch frequency
Example: with V
IN
= 12V, V
OUT
= 5V and I
OUT
= 2A
P
W
PW
PW
SW
BOOST
Q
=+
=+=
==
=+=
(. )()()
( )( / )( )( )( )
...
()( / )
.
(. ) (. ) .
015 2 5
12
101 10 12 2 12 500 10
025 061 086
5236
12
012
12 0 0015 5 0 003 0 033
2
93
2
Total power dissipation in the IC is given by:
P
TOT
= P
SW
+ P
BOOST
+ P
Q
= 0.86W + 0.12W + 0.03W = 1.01W
Thermal resistance for the LT3431 package is influenced
by the presence of internal or backside planes.
TSSOP (Exposed Pad) Package: With a full plane under the
TSSOP package, thermal resistance
JA
)
will be about
45°C/W.
To calculate die temperature, use the proper thermal
resistance number for the desired package and add in
worst-case ambient temperature:
T
J
= T
A
+ (θ
JA
• P
TOT
)
When estimating ambient, remember the nearby catch
diode and inductor will also be dissipating power:
P
VV V I
V
DIODE
F IN OUT LOAD
IN
=
( )( )( )
V
F
= Forward voltage of diode (assume 0.52V at 2A)
PW
DIODE
==
(. )( )()
.
052 12 5 2
12
061
Notice that the catch diode’s forward voltage contributes
a significant loss in the overall system efficiency. A larger,
lower V
F
diode can improve efficiency by several percent.
P
INDUCTOR
= (I
LOAD
)
2
(R
IND
)
R
IND
= Inductor DC resistance (assume 0.1)
P
INDUCTOR
(2)
2
(0.1) = 0.4W
Typical thermal resistance of the board is 5°C/W. Taking
the catch diode and inductor power dissipation into ac-
count and using the example calculations for LT3431
dissipation, the LT3431 die temperature will be estimated
as:
T
J
= T
A
+ (θ
JA
• P
TOT
) + [5 • (P
DIODE
+ P
INDUCTOR
)]
With the TSSOP package (θ
JA
= 45°C/W), at an ambient
temperature of 50°C:
T
J
= 50 + (45 • 1.01) + (5 • 1.01) = 101°C
Die temperature can peak for certain combinations of V
IN
,
V
OUT
and load current. While higher V
IN
gives greater
switch AC losses, quiescent and catch diode losses, a
lower V
IN
may generate greater losses due to switch DC
losses. In general, the maximum and minimum V
IN
levels
should be checked with maximum typical load current for
calculation of the LT3431 die temperature. If a more
accurate die temperature is required, a measurement of
the SYNC pin resistance (to GND) can be used. The SYNC
pin resistance can be measured by forcing a voltage no
greater than 0.5V at the pin and monitoring the pin current
over temperature in an oven. This should be done with
minimal device power (low V
IN
and no switching
(V
C
= 0V)) in order to calibrate SYNC pin resistance with
ambient (oven) temperature.
APPLICATIO S I FOR ATIO
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20
LT3431
sn3431 3431fs
Note: Some of the internal power dissipation in the IC, due
to BOOST pin voltage, can be transferred outside of the IC
to reduce junction temperature, by increasing the voltage
drop in the path of the boost diode D2. (see Figure␣ 9). This
reduction of junction temperature inside the IC will allow
higher ambient temperature operation for a given set of
conditions. BOOST pin circuitry dissipates power given
by:
P
VI V
V
DISS BOOST
OUT SW C
IN
()
•( / )•
=
36
2
Typically V
C2
(the boost voltage across the capacitor C2)
equals V
OUT
. This is because diodes D1 and D2 can be
considered almost equal, where:
V
C2
= V
OUT
– V
FD2
– (–V
FD1
) = V
OUT
.
Hence the equation used for boost circuitry power dissipa-
tion given in the previous Thermal Calculations section is
stated as:
P
VI V
V
DISS BOOST
OUT SW OUT
IN
()
•( / )•
=
36
Here it can be seen that Boost power dissipation increases
as the square of Vout. It is possible, however, to reduce
V
C2
below Vout to save power dissipation by increasing
the voltage drop in the path of D2. Care should be taken
that V
C2
does not fall below the minimum 3.3V Boost
voltage required for full saturation of the internal power
switch. For output voltages of 5V, V
C2
is approximately 5V.
During switch turn on, V
C2
will fall as the boost capacitor
C2 is dicharged by the boost pin. In a previous BOOST Pin
section, the value of C2 was designed for a 0.7V droop in
V
C2
= V
DROOP
. Hence, an output voltage as low as 4V
would still allow the minimum 3.3V for the boost function
using the C2 capacitor calculated. If a target output voltage
of 12V is required, however, an excess of 8V is placed
across the boost capacitor which is not required for the
boost function, but still dissipates additional power. What
is required is a voltage drop in the path of D2 to achieve
minimal power dissipation while still maintaining mini-
mum boost voltage across C2. A zener, D4, placed in
series with D2 (see Figure 9), drops voltage to C2.
Example : The BOOST pin power dissipation for a 20V input
to 12V output conversion at 2A is given by :
PW
BOOST
==
12 2 36 12
20
04
•( / )•
.
If a 7V zener D4 is placed in series with D2, then power
dissipation becomes :
PW
BOOST
==
12 2 36 5
20
0 167
•( / )•
.
For an FE package with thermal resistance of 45°C/W,
ambient temperature savings would be, T
(AMBIENT)
sav-
ings = 0.233W • 45°C/W = 11°C. The 7V zener should be
sized for excess of 0.233W operaton. The tolerances of the
zener should be considered to ensure minimum V
C2
ex-
ceeds 3.3V + V
DROOP
.
APPLICATIO S I FOR ATIO
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C2
C
F
D1
3431 F09
C3
R
C
C
C
D2
D2 D4
L1
C1
R1
R2
BOOST
V
IN
V
IN
LT3431
SHDN
SYNC
SW
BIAS
FB
V
C
GND
+
Figure 9. BOOST Pin, Diode Selection
Input Voltage vs Operating Frequency Considerations
The absolute maximum input supply voltage for the LT3431
is specified at 60V. This is based on internal semiconduc-
tor junction breakdown effects. The practical maximum
input supply voltage for the LT3431 may be less than 60V
due to internal power dissipation or switch minimum on
time considerations.
For the extreme case of an output short-circuit fault to
ground, see the section Short-Circuit Considerations.
21
LT3431
sn3431 3431fs
A detailed theoretical basis for estimating internal power
dissipation is given in the Thermal Calculations section.
This will allow a first pass check of whether an application’s
maximum input voltage requirement is suitable for the
LT3431. Be aware that these calculations are for DC input
voltages and that input voltage transients as high as 60V
are possible if the resulting increase in internal power
dissipation is of insufficient time duration to raise die
temperature significantly. For the FE package, this means
high voltage transients on the order of hundreds of milli-
seconds are possible. If LT3431 thermal calculations
show power dissipation is not suitable for the given
application, the LT3430 is a recommended alternative
since it is identical to the LT3431 but runs cooler at
200kHz.
Switch minimum on time is the other factor that may limit
the maximum operational input voltage for the LT3431 if
pulse-skipping behavior is not allowed. For the LT3431,
pulse-skipping may occur for V
IN
/(V
OUT
+ V
F
) ratios > 4.
(V
F
= Schottky diode D1 forward voltage drop, Figure 5.)
If the LT3430 is used, the ratio increases to 10. Pulse-
skipping is the regulator’s way of missing switch pulses to
maintain output voltage regulation. Although an increase
in output ripple voltage can occur during pulse-skipping,
a ceramic output capacitor can be used to keep ripple
voltage to a minimum (see output ripple voltage compari-
son for tantalum vs ceramic output capacitors, Figure 3).
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered—the worse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits, read the Layout Considerations section first.
Common layout errors that appear as stability problems
are distant placement of input decoupling capacitor and/
or catch diode, and connecting the V
C
compensation to a
ground track carrying significant switch current. In addi-
tion, the theoretical analysis considers only first order
non-ideal component behavior. For these reasons, it is
important that a final stability check is made with produc-
tion layout and components.
The LT3431 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 10.
The LT3431 can be considered as two g
m
blocks, the error
amplifier and the power stage.
APPLICATIO S I FOR ATIO
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Figure 10. Model for Loop Response
Figure 11 shows the overall loop response. At the V
C
pin,
the frequency compensation components used are:
R
C
= 3.3k, C
C
= 0.022µF and C
F
= 220pF. The output
capacitor used is a 100µF, 10V tantalum capacitor with
typical ESR of 100m.
The ESR of the tantalum output capacitor provides a
useful zero in the loop frequency response for maintain-
ing stability.
This ESR, however, contributes significantly to the ripple
voltage at the output (see Output Ripple Voltage in the
Applications Information section). It is possible to reduce
capacitor size and output ripple voltage by replacing the
+
1.22V
SW
V
C
LT3431
GND
3431 F10
R1
OUTPUT
ESR
C
F
C
C
R
C
R
O
200k
ERROR
AMPLIFIER
FB
R2
C1
R
LOAD
CURRENT MODE
POWER STAGE
g
m
= 2mho
g
m
=
2000µmho
+
TANTALUM
C
FB
ESL
C1
CERAMIC

LT3431IFE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi V, 3A, 500kHz Buck Sw Reg
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