PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 19 June 2014 24 of 48
NXP Semiconductors
PCA9626
24-bit Fm+ I
2
C-bus 100 mA 40 V LED driver
7.4 Active LOW output enable input
The active LOW output enable (OE) pin, allows enabling or disabling all the LED outputs
at the same time.
• When a LOW level is applied to OE pin, all the LED outputs are enabled as defined by
the CHASE register.
• When a HIGH level is applied to OE pin, all the LED outputs are high-impedance.
The OE
pin can be used as a synchronization signal to switch on/off several PCA9626
devices at the same time. This requires an external clock reference that provides blinking
period and the duty cycle.
The OE
pin can also be used as an external dimming control signal. The frequency of the
external clock must be high enough not to be seen by the human eye, and the duty cycle
value determines the brightness of the LEDs.
Remark: Do not use OE
as an external blinking control signal when internal global
blinking is selected (DMBLNK = 1, MODE2 register) since it results in an undefined
blinking pattern. Do not use OE
as an external dimming control signal when internal global
dimming is selected (DMBLNK = 0, MODE2 register) since it results in an undefined
dimming pattern.
Remark: During power-down, slow decay of voltage supplies may keep LEDs illuminated.
Consider disabling LED outputs using HIGH level applied to OE
pin.
7.5 Power-on reset
When power is applied to V
DD
, an internal power-on reset holds the PCA9626 in a reset
condition until V
DD
has reached V
POR
. At this point, the reset condition is released and the
PCA9626 registers and I
2
C-bus state machine are initialized to their default states (all
zeroes) causing all the channels to be deselected. Thereafter, V
DD
must be lowered below
0.2 V to reset the device.
7.6 Software reset
The Software Reset Call (SWRST Call) allows all the devices in the I
2
C-bus to be reset to
the power-up state value through a specific formatted I
2
C-bus command. To be performed
correctly, it implies that the I
2
C-bus is functional and that there is no device hanging the
bus.
The SWRST Call function is defined as the following:
1. A START command is sent by the I
2
C-bus master.
2. The reserved SWRST I
2
C-bus address ‘0000 011’ with the R/W bit set to ‘0’ (write) is
sent by the I
2
C-bus master.
3. The PCA9626 device(s) acknowledge(s) after seeing the SWRST Call address
‘0000 0110’ (06h) only. If the R/W
bit is set to ‘1’ (read), no acknowledge is returned to
the I
2
C-bus master.
4. Once the SWRST Call address has been sent and acknowledged, the master sends
2 bytes with 2 specific values (SWRST data byte 1 and byte 2):
a. Byte 1 = A5h: the PCA9626 acknowledges this value only. If byte 1 is not equal to
A5h, the PCA9626 does not acknowledge it.
