PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 19 June 2014 38 of 48
NXP Semiconductors
PCA9626
24-bit Fm+ I
2
C-bus 100 mA 40 V LED driver
[1] t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
[3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
IL
of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
[4] The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (t
f
) for the SDA output stage is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
f
.
[5] C
b
= total capacitance of one bus line in pF.
[6] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
Output port timing
t
d(SCL-Q)
delay time from SCL
to data output
SCL to LEDn;
MODE2[3] = 1;
outputs change on
ACK
-- - --450ns
t
d(SDA-Q)
delay time from SDA
to data output
SDA to LEDn;
MODE2[3] = 0;
outputs change on
STOP condition
-- - --450ns
Table 20. Dynamic characteristics
…continued
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode
I
2
C-bus
Fast-mode
Plus I
2
C-bus
Unit
Min Max Min Max Min Max
Fig 17. Definition of timing
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