PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 19 June 2014 25 of 48
NXP Semiconductors
PCA9626
24-bit Fm+ I
2
C-bus 100 mA 40 V LED driver
b. Byte 2 = 5Ah: the PCA9626 acknowledges this value only. If byte 2 is not equal to
5Ah, then the PCA9626 does not acknowledge it.
If more than 2 bytes of data are sent, the PCA9626 does not acknowledge any more.
5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and
correctly acknowledged, the master sends a STOP command to end the
SWRST Call: the PCA9626 then resets to the default value (power-up value) and is
ready to be addressed again within the specified bus free time (t
BUF
).
The I
2
C-bus master must interpret a non-acknowledge from the PCA9626 (at any time) as
a ‘SWRST Call Abort’. The PCA9626 does not initiate a reset of its registers. This
happens only when the format of the SWRST Call sequence is not correct.
7.7 Individual brightness control with group dimming/blinking
A 97 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used
to control individually the brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be
applied to the 4 LED outputs):
A lower 190 Hz fixed frequency signal with programmable duty cycle (8 bits,
256 steps) is used to provide a global brightness control.
A programmable frequency signal from 24 Hz to
1
10.73
Hz (8 bits, 256 steps) with
programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking
control.
Minimum pulse width for LEDn Brightness Control is 40 ns.
Minimum pulse width for Group Dimming is 20.48 s.
When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal has 2 pulses of the
LED Brightness Control signal (pulse width = N 40 ns, with ‘N’ defined in PWMx register).
This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 4 (8 pulses).
Fig 6. Brightness + Group Dimming signals
123456789101112 507
508
509
510
511
512
1234567891011
Brightness Control signal (LEDn)
M × 256 × 2 × 40 ns
with M = (0 to 255)
(GRPPWM Register)
N × 40 ns
with N = (0 to 255)
(PWMx Register)
256 × 40 ns = 10.24 μs
(97.6 kHz)
1234567812345678
Group Dimming signal
resulting Brightness + Group Dimming signal
256 × 2 × 256 × 40 ns = 5.24 ms (190.7 Hz)
002aab417
PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 19 June 2014 26 of 48
NXP Semiconductors
PCA9626
24-bit Fm+ I
2
C-bus 100 mA 40 V LED driver
8. Characteristics of the I
2
C-bus
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as control signals (see Figure 7
).
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 8
).
8.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 9
).
Fig 7. Bit transfer
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PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 19 June 2014 27 of 48
NXP Semiconductors
PCA9626
24-bit Fm+ I
2
C-bus 100 mA 40 V LED driver
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of 8 bits is followed by one acknowledge
bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the
master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 9. System configuration
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Fig 10. Acknowledgement on the I
2
C-bus
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PCA9626BS,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC LED DRIVER LINEAR DIM 48HVQFN
Lifecycle:
New from this manufacturer.
Delivery:
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