OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

NB3H5150MNTXG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
NB3H5150
www.onsemi.com
10
Table 9. DC CHARACTERISTICS
V
DD
= AV
DDn
= 3.3 V ±5% or 2.5 V ±5%; V
DDOn
= 3.3 V ±5% or 2.5 V ±5% or 1.8 V ±5%; GND = 0 V; T
A
= −40°C to 85°C
Symbol UnitMaxTypMinCharacteristic
LVCMOS OUTPUT; See Figure 12
V
OH
Output HIGH Voltage IOH = 12 mA V
DDO
– 0.5 V
DDO
V
V
OL
Output LOW Voltage IOL = 12 mA GND 0.5 V
R
OUT
Output Impedance 15
CRYSTAL INPUT DRIVEN SINGLE−ENDED (REFMODE = 1) (see Figure 3 and 5) (Note 9)
V
IHSE
CLK_XTAL1 Single−Ended Input HIGH Voltage 200 V
DD
mV
V
ILSE
CLK_XTAL1 Single−Ended Input LOW Voltage GND V
IHSE
− 200 mV
V
th
Input Threshold Reference Voltage Range 100 V
DD
− 100 mV
V
ISE
Single−Ended Input Voltage (V
IH
– V
IL
) 200 V
DD
mV
CRYSTAL INPUTS DRIVEN DIFFERENTIALLY (REFMODE = 1) (see Figure 4 and 6) (Note 11)
V
IHD
Differential Input HIGH Voltage 100 V
DD
mV
V
ILD
Differential Input LOW Voltage GND V
IHD
– 100 mV
V
ID
Differential Input Voltage (V
IHD
–
V
ILD
) 100 V
DD
mV
V
CMR
Input Common Mode Range (Differential Configuration)
(Note 10) (Figure 8)
50 V
DD
− 50 mV
I
IH
Input HIGH Current CLK_XTAL1 and CLKb_XTAL2 −10 10
A
I
IL
Input LOW Current CLK_XTAL1 & CLKb_XTAL2 −10 10
A
LVCMOS − CONTROL AND SDA & SCL/PD INPUTS
V
IH
Input HIGH Voltage for MMC & REFMODE Pins V
DD
= 3.3 V
V
DD
= 2.5 V
2.1
1.75
V
DD
V
V
IH
Input HIGH Voltage for SDA & SCL/PD Pins V
DD
= 3.3 V
V
DD
= 2.5 V
2.1
1.75
5.5 V
V
IL
Input LOW Voltage for Control Pins and SDA & SCL/PD V
DD
= 3.3 V
V
DD
= 2.5 V
GND
0.7
0.7
V
I
IH
Input HIGH Current −150 150
A
I
IL
Input LOW Current −150 150
A
VIH
tri
Tri−Level Input High Voltage (FSn pins)
V
DD
x 75% V
DD
V
V
DD
= 3.3 V 2.48 V
DD
V
DD
= 2.5 V 1.88 V
DD
VIM
tri
Tri−Level Input Med Voltage (FSn pins)
V
DD
x 40% V
DD
x 60%
V
V
DD
= 3.3 V 1.32 1.98
V
DD
= 2.5 V 1.00 1.67
VIL
tri
Tri−Level Input Low Voltage (FSn pins) GND
V
DD
x 25% V
V
DD
= 3.3 V 0.00 0.83
V
V
DD
= 2.5 V 0.00 0.63
RIN Input Impedance 10
k
CIN Input Capacitance − Crystal pins; REFMODE = H 2 pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
7. LVPECL Outputs loaded with 50 to V
DDO
– 2 V for proper operation.
8. LVPECL Output parameters vary 1:1 with V
DDO
.
9. V
IH, VIL, V
th
, and VISE parameters must be complied with simultaneously.
10.V
CMR
min varies 1:1 with GND, V
CMR
max varies 1:1 with V
DD
.
11. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
12.I
DD
/ V
DD
is independent of I
DDOn
/ V
DDOn
NB3H5150
www.onsemi.com
11
Table 10. AC CHARACTERISTICS
V
DD
= AV
DDn
= 3.3 V ±5% or 2.5 V ±5%; V
DDO
= 3.3V ±5% or 2.5 V ±5% or 1.8 V ±5%; GND = 0 V; T
A
= −40°C to 85°C (Note 13)
Symbol
Characteristic Min Typ Max Unit
f
CLKIN
External Clock / Crystal Input Frequency − PLL Mode −1000 ppm 25 +1000 ppm MHz
f
INBP
External Clock Input Frequency – PLL Bypass Mode I
2
C Mode;
f
in
= f
out
1 50 MHz
f
CLK1,2,3
CLK1, CLK2, CLK3 Typical Output Clock Frequencies; f
in
= 25 MHz
25
33.33
50
100
125
156.25
MHz
f
CLK4
CLK4 Outputs Typical Output Clock Frequencies; f
in
= 25 MHz
Resolution of 1 Hz Integer
Frac−N
66.66
106.23
133.33
155.52
161.1328
MHz
fSDA/SCL Serial Data and Clock Rates 100k bps
t
PWSCL
Serial Clock Pulse Width 1
s
t
w
Time SCL/PD Pin must be Held Low to “Wake−up” the Device 100 ns
t
DC
Output Clock Duty Cycle (Crystal or Reference Duty Cycle = 50%)
PLL Mode; <1 ns t
f
/ t
f
LVPECL f
out
= 156.25 MH
z
LVCMOS f
out
= 33.33 MH
z
PLL Bypass Mode; Input Duty Cycle = 50%, V
INPP
≥ 1.2 V
47.5
47.5
45
50
50
52.5
52.5
55
%
N
Phase Noise (Integer−N)
fout = 156.25 MHz, fin = 25 MHz Crystal, LVPECL 1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
−115
−130
−140
−145
−153
−153
dBc
N
Phase Noise (Integer−N)
fout = 100 MHz, fin = 25 MHz Crystal, LVCMOS 1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
−120
−136
−142
−145
−156
−156
dBc
N
Phase Noise (Frac−N)
fout = 155.52 MHz, fin = 25 MHz Crystal, LVPECL 1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
−115
−127
−131
−135
−152
−153
dBc
N
Phase Noise (Frac−N)
fout = 133.33 MHz, fin = 25 MHz Crystal, LVCMOS 1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
−117
−126
−126
−131
−153
−153
dBc
tjit()
RMS Phase Jitter − 25 MHz Crystal (Note 15)
Integration Range:12 kHz − 20 MHz
fout = 156.25 MHz, Integer CLK
n
fout = 155.52 MHz; Frac−N CLK4
300
1000
fs
tjit()
Additive RMS Phase Jitter (PLL Bypass in I
2
C Mode)
Integration Range:12 kHz − 5 MHz
fout = 25 MHz, CLK1
LVCMOS
50 fs
tpd Input to Output Propagation Delay (PLL Bypass in I
2
C Mode)
25 MHz
5 ns
NB3H5150
www.onsemi.com
12
Table 10. AC CHARACTERISTICS
V
DD
= AV
DDn
= 3.3 V ±5% or 2.5 V ±5%; V
DDO
= 3.3V ±5% or 2.5 V ±5% or 1.8 V ±5%; GND = 0 V; T
A
= −40°C to 85°C (Note 13)
Symbol UnitMaxTypMinCharacteristic
PSRR Ripple Induced Phase Spur Level
100 kHz & 1 MHz, 100 mVpp, Ripple Injected on V
DD
/AV
DDn
≤
100 MHz
−60
dBc
t
r
/
t
f
Output Rise/Fall Times (CLKnA/CLKnB), 20% − 80% of VDDO
n
fout = 156.25 Mhz LVPECL
fout = 33.33 Mhz @ VDDO = 3.3 V LVCMOS – 5 pF
120
500
200
800
300
1000
ps
V
INPP
Input Voltage Swing (Differential Configuration) (Note 14) 100 1200 mV
Stabilization
Time
Stabilization Time From Power−up VDD = 3.3 V to First Edge Out
Upon Reprogram – (Pin−Strap mode), Change of Configuration
Power−up to Static Output Levels – (Pin−Strap mode)
Power−up to I
2
C Ready
5
3
1
5
6
3
ms
t
PWRDWN
Time to Power Down, SCL/PD Low−to−High 50 100 200
s
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
13.Measured by using a 25 MHz crystal as clock source. All LVPECL outputs are loaded with an external R
L
= 50 to V
DDO
– 2 V (Figure 9);
LVCMOS outputs loaded with R
S
= 33 , C
L
= 5 pF, 5” 50 trace, (Figure 11).
14.Input and output voltage swings are single−ended measurements operating in a differential mode.
15.V
DD
= 3.3 V, V
DDO
= 2.5 V (LVPECL) or 1.8 V (LVCMOS).
Figure 3. Differential Input Driven Single−Ended Figure 4. Differential Inputs Driven Differentially
Figure 5. V
th
Diagram
CLK_XTAL1
V
DD
GND
V
IH
V
IHmin
V
IHmax
V
thmax
V
th
V
th
V
thmin
CLK_XTAL1
CLK
_XTAL2
V
th
V
th
CLK_XTAL1
CLK_XTAL2
V
ILmax
V
IL
V
ILmin
Figure 6. Differential Inputs Driven Differentially
V
IHD
V
ILD
V
ID
= |V
IHD(CLK)
− V
ILD(CLK)|
CLK_XTAL1
CLK
_XTAL2
V
IH
V
IL
Figure 7. V
CMR
Diagram
V
CMmin
V
CMmax
CLK_XTAL2
V
CMR
V
DD
GND
CLK_XTAL1
V
ILDmax
V
IHDmax
V
ID
= V
IHD
− V
ILD
V
ILDtyp
V
IHDtyp
V
ILDmin
V
IHDmin
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

NB3H5150MNTXG

Mfr. #:
Buy NB3H5150MNTXG
Manufacturer:
ON Semiconductor
Description:
Clock Generators & Support Products 3.3/2.5V PROGRAMMABL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet