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NB3H5150MNTXG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
NB3H5150
www.onsemi.com
7
I
2
C MODE: (see Table 6)
Some features that are not available in pin−strap mode can
be obtained in I2C mode, such as Output Enable/Disable,
By−Pass mode and Power−Down. In addition, output
frequency and output levels can also be I2C controlled.
The NB3H5150 I2C Programming Guide can be found on
the NB3H5150 web site. This application note provides
details on configuring the NB3H5150 by writing to registers
in the NB3H5150 with approved register files through the
I2C/SMBus interface.
http://www.onsemi.com/pub/Collateral/NB3H5150%20I2
C%20PROGRAMMING%20GUIDE%20%20..PDF
The user can select a Register File from the ON
Semiconductor website from the NB3H5150 I2C Register
Files folder. Additional Register Files can be generated by
the factory upon request.
http://www.onsemi.com/pub/Collateral/NB3H5150%20I2
C%20REGISTER%20FILES.ZIP
Prerequisites:
• SDA and SCL must be connected to I
2
C SMBus
• SDA must be logic High.
1. Upon device power−up.
a. All four frequencies and output type selections
will be preloaded according to the FSn pin
settings, but all four outputs will be held at
static LVPECL levels until the PLL has become
stable.
NOTE: After power up, changes to FS pins
will be blocked from controlling device
operation.
b. Once the PLL is stable, the Mixed Mode
Control pin (MMC) is checked:
i. If MMC is LOW, all CLK(n) outputs will
remain at static LVPECL levels.
ii. If MMC is HIGH and FS4A is LOW, CLK1,
CLK2, and CLK3 outputs will remain at
static LVPECL levels.
CLK4A/4B output frequency and output
levels will become active after PLL
stabilization time according to FS4A and
FS4B pin selection in Table 4.
After power up, changes to all pins will be
ignored.
iii. If MMC is HIGH and FS4A MID or HIGH,
CLK1, CLK2, and CLK3 output frequency
and type will become active after PLL
stabilization time according to their
respective FS1, FS2 and FS3 pin selection in
Table 3.
CLK4A/4B outputs remain at Static
LVPECL Levels.
After power up, changes to all pins will be
ignored except the SDA and SCL inputs.
iv. The FS4A and FS4B pins set the bus address
when MMC pin is LOW (see Table 6, I2C
Device Address Table).
c. The I
2
C interface can now be used to load
register files into the NB3H5150. In I
2
C Mode,
configuration of Output Enables, output
frequency, output levels of each output, specific
block power−down control, bypass mode, etc.
are all possible.
d. Any outputs which were held in static level
mode (described above) will be released for
operation.
CLK(n) outputs will be active at the programmed
frequencies and levels.
CLK(n) outputs will react to any subsequent changes to the
I
2
C bus.
If any output channel is not programmed, then output is
loaded from FSn pins.
A Power Cycle will clear all previous register information
and I
2
C mode will repeat to number 1 in the power up
sequence.
To simplify device configuration, ON Semiconductor
provides desktop software, that can be downloaded from
http://www.onsemi.com/pub/Collateral/NB3H5150_GUI.
ZIP which will operate in conjunction with the NB3H5150
evaluation board (EVB). The NB3H5150 GUI manual can
also be found on the web site.
When the software is connected to an NB3H5150 EVB,
it can control the selection of numerous clock output
frequencies for each of the four CLK outputs and the output
type as well as Output Enable/Disable.
I
2
C Programmable Selection of Output Frequency and
Level
Table 5 contains register files that produce various
combinations of output frequencies and output types.
Each register file can be loaded from GUI into the demo
board, or loaded into the I
2
C port of the device.
NB3H5150
www.onsemi.com
8
Table 5. I
2
C OUTPUT FREQUENCY AND MODE SELECTION REGISTERS
Reg.FILE# CLK1 (MHz) CLK2 (MHz) CLK3 (MHz) CLK4 (MHz)
1 100 LVPECL 125 LVPECL 156.25 LVPECL 155.52 LVPECL
2 100 LVPECL 100 LVPECL 125 LVPECL 125 LVPECL
3 25 LVCMOS Disabled 156.25 LVPECL 70.656 LVPECL
4 25 LVCMOS Disabled 100 LVPECL Disabled
5 25 LVCMOS 156.25 LVPECL 156.25 LVPECL 156.25 LVPECL
6 25 LVCMOS 100 LVPECL 100 LVPECL Disabled
7 156.25 LVPECL 156.25 LVPECL 156.25 LVPECL 156.25 LVPECL
8 50.00 LVPECL 125.00 LVPECL 156.25 LVPECL 133.33 LVCMOS
9 Bypass LVCMOS 156.25 LVPECL 100.00 LVPECL 156.25 LVPECL
10 Bypass LVPECL 156.25 LVPECL 156.25 LVPECL 156.25 LVPECL
11 Bypass LVCMOS 156.25 LVPECL 156.25 LVPECL 156.25 LVPECL
12 Disabled Disabled Disabled Disabled
Table 6. SDA, SCL AND MMC CONTROL PINS FOR OUTPUT FUNCTION
Mode SDA SCL/PD MMC Comments
Outputs (Note 2)
CLK1, CLK2,
CLK3
CLK4
Pin−Strap FS Mode L L X Normal Operation Toggle per Table 3 Toggle per Table 4
Power−Down L H X Off Off
I
2
C
(Note 3)
Dynamic Dynamic X
I2C Mode Is Active After
Mixed Mode Power−Up
Sequence
Active Per I2C Map Active Per I
2
C Map
Mixed Mode
H
Note 4
H
Note 4
L
Static LVPECL
Logic Levels
Static LVPECL
Logic Levels
H
Note 4
H
Note 4
H
FS4A = L
Static LVPECL
Logic Levels
Active per Table 4
H
Note 4
H
Note 4
H
FS4A =
M or H
Active per Table 3
Static LVPECL
Logic Levels
2. All outputs are static until after the PLL is stable.
3. Any changes to the device configuration after power−up are made by reading and writing to registers through the I2C interface.
4. Don’t care state unless device address is matched by controller address.
X = don’t care
Table 7. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
Charge Device Model
> 2 kV
> 150 V
> 500 V
Moisture Sensitivity (Note 5) 32−QFN Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 245, 894
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
5. For additional information, see Application Note AND8003/D.
NB3H5150
www.onsemi.com
9
Table 8. MAXIMUM RATINGS
Symbol Parameter Condition Rating Unit
V
DD
Positive Power Supply – Core GND = 0 V 3.63 V
AV
DDn
Positive Power Supply – Analog GND = 0 V 3.63 V
V
DDOn
Positive Power Supply – Outputs GND = 0 V 3.63 V
V
IO
Positive Input/Output Voltage GND = 0 V −0.5 to V
DD
+0.5
V
V
I
Positive Input Voltage SDA and SCL GND = 0 V 5.5 V
T
A
Operating Temperature Range QFN−32 −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
θ
J
Maximum Junction Temperature 125 °C
θ
JA
Thermal Resistance (Junction−to−Ambient) (Note 6) QFN−32
QFN−32
0 lfpm
500 lfpm
31
27
°C/W
°C/W
θ
JC
Thermal Resistance (Junction−to−Case) (Note 6) QFN−32 12 °C/W
T
J
Maximum Junction Temperature 125 °C
T
sol
Wave Solder Pb−Free, 10 sec 265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
6. JEDEC standard multilayer board – 2S2P (2 signal, 2 power).
Table 9. DC CHARACTERISTICS
V
DD
= AV
DDn
= 3.3 V ±5% or 2.5 V ±5%; V
DDOn
= 3.3 V ±5% or 2.5 V ±5% or 1.8 V ±5%; GND = 0 V; T
A
= −40°C to 85°C
Symbol
Characteristic Min Typ Max Unit
POWER SUPPLY / CURRENT (Note 12)
V
DD
/AV
DDn
V
DDOn
Core Power Supply V
DD
= AV
DDn
= 3.3 V
V
DD
= AV
DDn
= 2.5 V
Output Power Supply V
DDOn
= 3.3 V
V
DDOn
= 2.5 V
V
DDOn
= 1.8 V (LVCMOS only)
3.135
2.375
3.135
2.375
1.71
3.3
2.5
3.3
2.5
1.8
3.465
2.625
3.465
2.625
1.89
V
I
DD
/I
ADDn
Core and Input Power Supply Current for V
DD
and A
VDDn
V
DD
= 3.3 V CLK4 Integer
CLK4 Frac−N
V
DD
= 2.5 V CLK4 Integer
CLK4 Frac−N
60
75
55
70
75
90
70
85
mA
I
DDOn
Output Buffer Power Supply Current for V
DDOn
Incremental I
DDO
Current by One Output Bank and Output Type
LVPECL − One differential LVPECL output pair (CLKnA & CLKnB)
Frequency Independent V
DDO
= 3.3 V
V
DDO
= 2.5 V
LVCMOS − Two LVCMOS outputs (CLKnA & CLKnB)
f = 50 MHz V
DDO
= 3.3 V
V
DDO
= 2.5 V
V
DDO
= 1.8 V
40
40
20
17
15
50
50
25
23
21
mA
I
DD
PWRDN Power Down Current SCL/PD = High 100
A
LVPECL OUTPUTS (Note 7 and 8) V
DDOn
= 3.3 V ±5% or 2.5 V ±5%; See Figure 10
V
OH
Output HIGH Voltage V
DDO
− 1.200 V
DDO
− 0.895 V
V
OL
Output LOW Voltage V
DDO
− 2.000 V
DDO
− 1.600 V
V
SWING
V
OUT
PK−PK
Voltage Swing 550 720 900 mV
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

NB3H5150MNTXG

Mfr. #:
Buy NB3H5150MNTXG
Manufacturer:
ON Semiconductor
Description:
Clock Generators & Support Products 3.3/2.5V PROGRAMMABL
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New from this manufacturer.
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