NB3H5150MNTXG Datasheet NB3H5150MNTXG | P4-P6

NB3H5150

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Table 1. PIN DESCRIPTION

Pin DescriptionI/OName

32 CLK_XTAL1 Crystal or

LVTTL/LVCMOS

or LVPECL/LVDS

Input

Crystal Input or Single−Ended or Differential Clock Input; If CLK_XTAL1 is used as

single−ended input, CLK

_XTAL2 must be connected to ground. See Table 2.

EP Exposed Pad Ground Ground – Negative Power Supply is connected via the Exposed Pad .

The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die

for improved heat transfer out of package. The exposed pad must be attached to a heat

sinking conduit. The pad is electrically connected to the die,carries all power supply return

currents and must be electrically connected to GND.

1. All VDD, AVDDn, VDDOn, EP (GND) pins must be externally connected to a power supply for proper operation. VDD and AVDDn must all

be at the same voltage.

NB3H5150 BASIC OPERATION

Introduction

The NB3H5150 is a Multi−Rate Clock Generator. The

clock reference for the PLL can be either a 25 MHz crystal,

single−ended LVCMOS or LVTTL signal or a differential

LVPECL, LVDS or HCSL signal.

There are two modes of operation for the NB3H5150,

Pin−Strap and I

In the Pin−Strap Mode, the user can select any of the

defined output frequencies for each of the four output banks

as specified in Tables 3 and 4 via the three−level Frequency

Select pins: FS1, FS2, FS3, FS4A and FS4B.

In the I

C mode, the user can select one of the approved

selection of output frequencies and level combinations,

output enable/disable and bypass mode functions.

CLKnA & CLKnB − Output Frequency and Output

Level Selection

There are four output banks: CLK1A&B, CLK2A&B and

CLK3A&B are integer only divider outputs, whereas

CLK4A&B can be set or programmed as an integer or

fractional divider.

The output levels for each output bank can be LVPECL

(differential) or LVCMOS (two single−ended). Output

Enable / Disable functions are available in I

C only.

CLK1, 2, 3 and 4 outputs are not phase−aligned, in PLL

or PLL bypass modes.

Power−On Output Default

Upon power−up, all four outputs will be forced to and held

at static LVPECL levels (CLKnA = Low, CLKnB = High)

until the PLL is stable. The PLL will be stable before any of

the output Clocks, CLKnx, are enabled.

SDA & SCL/PD - Serial Data Interface – I2C

The NB3H5150 incorporates a two−wire Serial Data

Interface to expand the flexibility and function of the

NB3H5150 clock generator.

The I

C interface pins, SCL and SDA, are used to load

These register files will configure the internal registers to

achieve an expanded selection of output frequencies and

levels combinations for each of the four output blocks.

Subsequent changes in the registers can then be performed

with another register file to modify any of the output

frequencies or output modes.

OE, Output Enable

An OE, Output Enable/Disable function is available only

in the I

C mode by loading a register file, such that any

individual output bank can be enabled or disabled. In

LVCMOS modes outputs will disable LOW for CLKnA and

CLKnB, while the LVPECL mode outputs will disable

CLKnA = Low and CLKnB = High.

Mixed Mode Control (MMC)

In the I

C mode, the Mixed Mode Control (MMC) pin is

used for a combination of FSn settings and I

2C settings to

control the CLK(n) outputs’ function as defined in Table 7.

REFMODE – Select a Crystal or External Clock Input

Interface (See Table 2)

The REFMODE pin will select the reference input for the

CLK_XTAL1 and CLK

_XTAL2 pins to use either a crystal,

an overdriven single−ended or differential input.

When using a crystal, set the REFMODE pin to a LOW.

The CLK_XTAL1 and CLK

_XTAL2 input pins will accept

a 25 MHz crystal.

When using a direct−coupled differential input, set the

REFMODE pin to a HIGH.

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When REFMODE is HIGH, the CLK_XTAL1 and

CLK

_XTAL2 differential input pins have internal AC

coupling capacitors selected with self−bias circuity for the

differential input buffer. This differential buffer will directly

accept any differential signal including LVPECL, LVDS,

HCSL or CML. Drive the CLK_XTAL1 pin with the true

signal and the CLK

_XTAL2 pin with the complementary

signal.

When overdriving the CLK_XTAL1 input pin with a

single−ended signal set REFMODE to a HIGH, and connect

CLK

_XTAL2 to Ground. The input has internal AC

coupling capacitor with self−bias circuitry.

Table 2. CRYSTAL INPUT INTERFACE AND REFMODE TRUTH TABLE

Input Mode Crystal/External Clock REFMODE CLK_XTAL1 CLKb_XTAL2

Crystal LOW Use a Crystal Use a Crystal

Any Differential Input HIGH Overdrive with True Input Overdrive with Complementary Input

Single−Ended Input HIGH Overdrive Connect to Ground

LVCMOS Outputs

LVCMOS outputs are powered with VDDOn = 3.3 V,

2.5 V or 1.8 V

A 33  series terminating resistor may be used on each

clock output if the metal trace is longer than one inch.

Any unused LVCMOS output can be left floating, but

there should be no metal trace attached to the package pin.

LVPECL Differential Outputs

The differential LVPECL outputs are powered with

VDDO = 3.3 V or 2.5 V and must be properly loaded. See

Figure 10.

Any unused differential output pair should either be left

floating or terminated.

REF Out

In the PLL bypass mode available via I

C, the input

reference frequency can be routed to CLK1A and CLK1B as

phase aligned LVCMOS or differential LVPECL outputs

with the same frequency. The output frequency and duty

cycle equals the input frequency and duty cycle.

Power Supplies

The NB3H5150 has several power supply pins:

• VDD is the supply voltage for the input and digital core

circuitry.

• AVDD1, AVDD2 and AVDD3 powers the core analog

circuits. VDD = AVDD1 = AVDD2 = AVDD3.

• VDDO1, VDDO2, VDDO3 and VDDO4 are individual

power supplies for each of the four CLKnA/B output

banks.

Upon power−up, all four VDDOn pins must be connected

to a power supply, even if only one output is being used.

Any combination of VDD and VDDOn power supply

voltages is allowed.

A power supply filtering scheme in Figure 8 is

recommended for best device performance.

When all VDD, AVDDn and VDDOn pins reach their

minimum voltage per Table 10, the NB3H5150 will operate

at the proper output frequencies.

EP Exposed Pad

The exposed pad on the bottom side of the package must

be connected to Ground.

LDO Pins

The NB3H5150 has integrated low noise 1.8 V

Low−Drop−Out (LDO) voltage regulators which provide

power internal to the NB3H5150.

The LDOs require decoupling capacitors in the range of

1 F to 10 F for compensation and high frequency PSR.

When powered−down, the device turns off the LDOs and

enters a low power shutdown mode consuming less than

1 mA.

FTM

This is a Factory Test Mode pin and must be connected to

the Ground of the application for proper operation.

PIN−STRAP / FSn Frequency Select MODE: (see

Tables 3 and 4)

The NB3H5150 can be configured to operate in pin−strap

mode where the control pins FSnA/B can be set to generate

the necessary clock outputs of the device.

Prerequisites:

♦ SDA and SCL/PD must be Low at all times while in

pin−strap mode to enable FS control. If SDA ever

goes High, pin−strap is exited and the only way to

go back is to power cycle the device.

♦ Mixed Mode Control pin (MMC) level will be

IGNORED.

Sequencing:

1. Upon device power−up (assuming SCL is LOW)

a. All four CLK(n) frequency and output type

selections will be pre−loaded according to the

FS pin settings, but all four outputs will be held

at static LVPECL levels (CLKnA = Low,

CLKnB = High) until the PLL has become

stable.

b. After the PLL is stable, all CLK(n) output type

selections (i.e. LVPECL or LVCMOS) will

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become effective and will begin to output the

selected frequencies.

2. Subsequent changes to any FS pin(s) will cause

the associated CLK(n) output(s) to momentarily

go to static levels, and then to resume at the new

frequency; CLK(n) will follow the FS(n) pin

programmable Tables 3 and 4 for output

frequencies and interface levels.

Note that in changing from LVPECL to LVCMOS

(or vice−versa), output logic levels cannot be

guaranteed. This is because the receiver inputs are

not likely to change in a given application, and the

LVPECL output loading in the application will

also not change. It is logical to presume that the

output type will be predetermined and fixed.

Therefore, in a system/application, the user should

be aware that subsequent change to the FS pin

should only change frequency, and not output type.

3. Power off/on cycle will repeat the entire sequence

4. Power Down

To initiate the Power−Down mode, the SDA pin

must be LOW and remain LOW. If the SCL/PD

pin is taken HIGH at any time, the device enters a

complete power−down mode with a current

consumption of less than 1 mA for the entire

device. When SCL/PD is subsequently taken

LOW, the device will function as though power

were removed and re−applied. That is, sequencing

will begin at #1.

Power−down is also available via I

C with a

FS(n) Pin Programmable Selection of Output Frequencies and Levels

Table 3. NB3H5150 − CLK1A:3A & CLK1B:3B OUTPUT FREQUENCY SELECT

TABLE WITH 25 MHz CRYSTAL

Logic Level

FS1 (CLK1)

(MHz)

FS2 (CLK2)

(MHz)

FS3 (CLK3)

(MHz)

Low 50.00 (LVCMOS) 156.25 (LVPECL) 156.25 (LVPECL)

Mid / Float* 33.33 (LVCMOS) 25.00 (LVPECL) 125.00 (LVCMOS)

High 25.00 (LVCMOS) 125.00 (LVPECL) 100.00 (LVPECL)

*(Default)

Table 4. NB3H5150 − CLK4A & CLK4B OUTPUT FREQUENCY SELECT TRUTH

TABLE (MHz) WITH 25 MHz CRYSTAL*

FS4A FS4B CLK4 (MHz) Divider Type

Low Low 33.33 (LVCMOS) Integer

Low Mid / Float 66.66 (LVCMOS) Fractional

Low High 133.33 (LVCMOS) Fractional

Mid / Float Low 155.52 (LVPECL) Fractional

Mid / Float* Mid / Float* 156.25 (LVPECL) Integer

Mid / Float High 125.00 (LVPECL) Integer

High Low 106.25 (LVPECL) Fractional

High Mid / Float 100.00 (LVCMOS) Integer

High High 161.1328 (LVPECL) Fractional

*(Default)

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NB3H5150MNTXG

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