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AD7468BRTZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
AD7466/AD7467/AD7468
Rev. C | Page 22 of 28
SERIAL INTERFACE
Figure 29, Figure 30, and Figure 31 show the timing diagrams
for serial interfacing to the AD7466/AD7467/AD7468. The
serial clock provides the conversion clock and controls the
transfer of information from the ADC during a conversion.
The part begins to power up on the
CS
falling edge. The falling
edge of
CS
puts the track-and-hold into track mode and takes
the bus out of three-state. The conversion is also initiated at this
point. On the third SCLK falling edge after the
CS
falling edge,
the part should be powered up fully at Point B, as shown in
Figure 29, and the track-and-hold returns to hold.
For the AD7466, the SDATA line goes back into three-state and
the part enters power-down on the 16th SCLK falling edge. If
the rising edge of
CS
occurs before 16 SCLKs elapse, the
conversion terminates, the SDATA line goes back into three-
state, and the part enters power-down; otherwise SDATA
returns to three-state on the 16th SCLK falling edge, as shown
in
Figure 29. Sixteen serial clock cycles are required to perform
the conversion process and to access data from the AD7466.
For the AD7467, the 14th SCLK falling edge causes the SDATA
line to go back into three-state, and the part enters power-down.
If the rising edge of
CS
occurs before 14 SCLKs elapse, the con-
version terminates, the SDATA line goes back into three-state,
and the AD7467 enters power-down; otherwise SDATA returns
to three-state on the 14th SCLK falling edge, as shown in
Figure 30.
Fourteen serial clock cycles are required to perform the
conversion process and to access data from the AD7467.
For the AD7468, the 12th SCLK falling edge causes the SDATA
line to go back into three-state, and the part enters power-
down. If the rising edge of
CS
occurs before 12 SCLKs elapse,
the conversion terminates, the SDATA line goes back into three-
state, and the AD7468 enters power-down; otherwise SDATA
returns to three-state on the 12th SCLK falling edge, as shown
in
Figure 31. Twelve serial clock cycles are required to perform
the conversion process and to access data from the AD7468.
CS
going low provides the first leading zero to be read in by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges, beginning with the second
leading zero; thus, the first clock falling edge on the serial clock
has the first leading zero provided and also clocks out the
second leading zero. For the AD7466, the final bit in the data
transfer is valid on the 16th SCLK falling edge, having been
clocked out on the previous (15th) SCLK falling edge.
In applications with a slow SCLK, it is possible to read in data
on each SCLK rising edge. In such a case, the first falling edge
of SCLK after the
CS
falling edge clocks out the second leading
zero and can be read in the following rising edge. If the first
SCLK edge after the
CS
falling edge is a falling edge, the first
leading zero that was clocked out when
CS
went low is missed,
unless it is not read on the first SCLK falling edge. The 15th
falling edge of SCLK clocks out the last bit, and it can be read in
the following rising SCLK edge.
If the first SCLK edge after the
CS
falling edge is a rising edge,
CS
clocks out the first leading zero, and it can be read on the SCLK
rising edge. The next SCLK falling edge clocks out the second
leading zero, and it can be read on the following rising edge.
SCLK
t
2
t
3
t
4
t
7
t
5
t
8
t
CONVERT
t
QUIET
DB11 DB10 DB2 DB1 DB0
B
4 LEADING ZEROS
13 14 15 16
t
1
THREE-STATE
THREE-STATE
S
DAT
A
CS
5
43
2
1
02643-030
t
6
12 BITS OF DATA
0
0
00
Figure 29. AD7466 Serial Interface Timing Diagram
t
QUIET
t
1
SCLK
S
DAT
A
4 LEADING ZEROS
THREE-STATE
THREE-STATE
10 BITS OF DATA
B
12345 1314
DB9 DB8 DB0
t
2
t
3
t
4
t
7
t
5
t
8
t
6
t
CONVERT
02643-031
CS
0
0
00
Figure 30. AD7467 Serial Interface Timing Diagram
AD7466/AD7467/AD7468
Rev. C | Page 23 of 28
t
1
SCLK
S
DAT
A
B
1 2 3 4 11 12
t
2
t
6
t
CONVERT
t
QUIET
4 LEADING ZEROS
THREE-STATE
THREE-STATE
8 BITS OF DATA
DB7 DB0
t
3
t
4
t
7
t
5
t
8
CS
02643-032
0
0
00
Figure 31. AD7468 Serial Interface Timing Diagram
MICROPROCESSOR INTERFACING
The serial interface on the AD7466/AD7467/AD7468 allows
the parts to be connected directly to many different micro-
processors. This section explains how to interface the AD7466/
AD7467/AD7468 with some of the more common microcontroller
and DSP serial interface protocols.
AD7466/AD7467/AD7468 to TMS320C541 Interface
The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7466/AD7467/AD7468. The
CS
input allows easy inter-
facing between the TMS320C541 and the AD74xx devices,
without requiring any glue logic. The serial port of the
TMS320C541 is set up to operate in burst mode (FSM = 1
in the serial port control register, SPC) with internal CLKX
(MCM = 1 in the SPC register) and internal frame signal
(TXM = 1 in the SPC register), so both pins are configured as
outputs. For the AD7466, the word length should be set to
16 bits (FO = 0 in the SPC register). The standard synchronous
serial port interface in this DSP allows only frames with a word
length of 16 bits or 8 bits. Therefore, for the AD7467 and
AD7468 where 14 and 12 bits are required, the FO bit also
would be set up to 16 bits. In these cases, the user should keep
in mind that the last 2 bits and 4 bits for the AD7467 and
AD7468, respectively, are invalid data as the SDATA line goes
back into three-state on the 14th and 12th SCLK falling edge.
To summarize, the values in the SPC register are FO = 0,
FSM = 1, MCM = 1, and TXM = 1.
Figure 32 shows the connection diagram. For signal processing
applications, it is imperative that the frame synchronization
signal from the TMS320C541 provide equidistant sampling.
AD7466/
AD7467/
AD7468
1
SCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
SDATA
TMS320C541
1
CLKX
CLKR
DR
FSX
FSR
02643-033
CS
Figure 32. Interfacing to the TMS320C541
AD7466/AD7467/AD7468 to ADSP-218x Interface
The ADSP-218x family of DSPs is interfaced directly to the
AD7466/AD7467/AD7468 without any glue logic. The SPORT
control register must be set up as described in
Table 9.
Table 9. SPORT Control Register Setup
Setting Description
TFSW = RFSW = 1 Alternate framing
INVRFS = INVTFS = 1 Active low frame signal
DTYPE = 00 Right-justify data
ISCLK = 1 Internal serial clock
TFSR = RFSR = 1 Frame every word
IRFS = 0 Sets up RFS as an input
ITFS = 1 Sets up TFS as an output
SLEN = 1111 16 bits for the AD7466
SLEN = 1101 14 bits for the AD7467
SLEN = 1011 12 bits for the AD7468
AD7466/AD7467/AD7468
Rev. C | Page 24 of 28
The connection diagram in Figure 33 shows how the ADSP-218x
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode, and the SPORT control register is set
up as described. The frame synchronization signal generated on
the TFS is tied to
CS
, and as with all signal processing applica-
tions, equidistant sampling is necessary. However, in this example,
the timer interrupt is used to control the sampling rate of the
ADC and, under certain conditions, equidistant sampling might
not be achieved.
The timer registers, for example, are loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and, there-
fore, the reading of data. The frequency of the serial clock is set
in the SCLKDIV register. When the instruction to transmit with
TFS is given (that is, AX0 = TX0), the state of the SCLK is
checked. The DSP waits until the SCLK goes high, low, and high
again before transmission starts. If the timer and SCLK values
are chosen such that the instruction to transmit occurs on or
near the rising edge of SCLK, the data can be transmitted, or it
can wait until the next clock edge.
For example, the ADSP-2181 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained, and eight master clock periods
elapse for every SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs occur between interrupts and,
subsequently, between transmit instructions. This situation
results in nonequidistant sampling as the transmit instruction is
occurring on an SCLK edge. If the number of SCLKs between
interrupts is a whole integer figure of N, equidistant sampling is
implemented by the DSP.
AD7466/
AD7467/
AD7468
1
SCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
SDATA
ADSP-218x
1
SCLK
DR
RFS
TFS
02643-034
CS
Figure 33. Interfacing to the ADSP-218x
AD7466/AD7467/AD7468 to DSP563xx Interface
The connection diagram in Figure 34 shows how the AD7466/
AD7467/AD7468 can be connected to the synchronous serial
interface (SSI) of the DSP563xx family of DSPs from Motorola.
The SSI is operated in synchronous mode and normal mode
(SYN = 1 and MOD = 0 in Control Register B, CRB) with an
internally generated word frame sync for both Tx and Rx
(Bit FSL1 = 0 and Bit FSL0 = 0 in the CRB register). Set the
word length in Control Register A (CRA) to 16 by setting Bits
WL2 = 0, WL1 = 1, and WL0 = 0 for the AD7466. The word
length for the AD7468 can be set to 12 bits (WL2 = 0, WL1 = 0,
and WL0 = 1). This DSP does not offer the option for a 14-bit
word length, so the AD7467 word length is set up to 16 bits like
the AD7466 word length. In this case, the user should keep in
mind that the last two bits are invalid data because the SDATA
goes back into three-state on the 14th SCLK falling edge.
The frame sync polarity bit (FSP) in the CRB register can be set
to 1, which means the frame goes low and a conversion starts.
Likewise, by means of Bits SCD2, SCKD, and SHFD in the CRB
register, it is established that Pin SC2 (the frame sync signal)
and Pin SCK in the serial port are configured as outputs, and
the most significant bit (MSB) is shifted first. To summarize,
MOD = 0
SYN = 1
WL2, WL1, WL0 depend on the word length
FSL1 = 0, FSL0 = 0
FSP = 1, negative frame sync
SCD2 = 1
SCKD = 1
SHFD = 0
For signal processing applications, it is imperative that the
frame synchronization signal from the DSP563xx provides
equidistant sampling.
AD7466/
AD7467/
AD7468
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
DSP563xx
1
SDATA
SRD
SCLK SCK
SC2
02643-035
CS
Figure 34. Interfacing to the DSP563xx
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AD7468BRTZ-REEL7

Mfr. #:
Buy AD7468BRTZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 1.6V MicroPwr 8-Bit
Lifecycle:
New from this manufacturer.
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