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AD7468BRTZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
AD7466/AD7467/AD7468
Rev. C | Page 7 of 28
AD7468
V
DD
= 1.6 V to 3.6 V, f
SCLK
= 3.4 MHz, f
SAMPLE
= 100 kSPS, unless otherwise noted. T
A
= T
MIN
to T
MAX
, unless otherwise noted.
The temperature range for the B version is −40°C to +85°C.
Table 3.
Parameter B Version Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Maximum/minimum specifications apply as typical figures
when V
DD
= 1.6 V, f
IN
= 30 kHz sine wave
Signal-to-Noise and Distortion (SINAD) 49 dB min See the Terminology section
Total Harmonic Distortion (THD) −66 dB max See the Terminology section
Peak Harmonic or Spurious Noise
(SFDR)
−66 dB max See the
Terminology section
Intermodulation Distortion (IMD) fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section
Second-Order Terms −77 dB typ
Third-Order Terms −77 dB typ
Aperture Delay 10 ns typ
Aperture Jitter 40 ps typ
Full Power Bandwidth 3.2 MHz typ @ 3 dB, 2.5 V ≤ V
DD
≤ 3.6 V
1.9 MHz typ @ 3 dB, 1.6 V ≤ V
DD
≤ 2.2 V
750 kHz typ @ 0.1 dB, 2.5 V ≤ V
DD
≤ 3.6 V
450 kHz typ @ 0.1 dB, 1.6 V ≤ V
DD
≤ 2.2 V
DC ACCURACY
Maximum specifications apply as typical figures when
V
DD
= 1.6 V
Resolution 8 Bits
Integral Nonlinearity ±0.2 LSB max See the Terminology section
Differential Nonlinearity ±0.2 LSB max
Guaranteed no missed codes to 8 bits; see the
Terminology
section
Offset Error ±0.1 LSB max See the Terminology section
Gain Error ±0.1 LSB max See the Terminology section
Total Unadjusted Error (TUE) ±0.3 LSB max See the Terminology section
ANALOG INPUT
Input Voltage Ranges 0 to V
DD
V
DC Leakage Current ±1 μA max
Input Capacitance 20 pF typ
LOGIC INPUTS
Input High Voltage, V
INH
0.7 × V
DD
V min 1.6 V ≤ V
DD
< 2.7 V
2 V min 2.7 V ≤ V
DD
≤ 3.6 V
Input Low Voltage, V
INL
0.2 × V
DD
V max 1.6 V ≤ V
DD
< 1.8 V
0.3 × V
DD
V max 1.8 V ≤ V
DD
< 2.7 V
0.8 V max 2.7 V ≤ V
DD
≤ 3.6 V
Input Current, I
IN
, SCLK Pin ±1 μA max Typically 20 nA, V
IN
= 0 V or V
DD
Input Current, I
IN
, CS Pin
±1 μA typ
Input Capacitance, C
IN
10 pF max Sample tested at 25°C to ensure compliance
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DD
− 0.2 V min I
SOURCE
= 200 μA; V
DD
= 1.6 V to 3.6 V
Output Low Voltage, V
OL
0.2 V max I
SINK
= 200 μA
Floating-State Leakage Current ±1 μA max
Floating-State Output Capacitance 10 pF max Sample tested at 25°C to ensure compliance
Output Coding
Straight (natural)
binary
CONVERSION RATE
Conversion Time 2.94 μs max 10 SCLK cycles with SCLK at 3.4 MHz
Throughput Rate 320 kSPS max See the Serial Interface section
AD7466/AD7467/AD7468
Rev. C | Page 8 of 28
Parameter B Version Unit Test Conditions/Comments
POWER REQUIREMENTS
V
DD
1.6/3.6 V min/max
I
DD
Digital inputs = 0 V or V
DD
Normal Mode (Operational) 190 μA max V
DD
= 3 V, f
SAMPLE
= 100 kSPS
155 μA max V
DD
= 2.5 V, f
SAMPLE
= 100 kSPS
120 μA max V
DD
= 1.8 V, f
SAMPLE
= 100 kSPS
Power-Down Mode 0.1 μA max SCLK on or off, typically 8 nA
Power Dissipation See the Power Consumption section
Normal Mode (Operational) 0.57 mW max V
DD
= 3 V, f
SAMPLE
= 100 kSPS
0.4 mW max V
DD
= 2.5 V, f
SAMPLE
= 100 kSPS
0.2 mW max V
DD
= 1.8 V, f
SAMPLE
= 100 kSPS
Power-Down Mode 0.3 μW max V
DD
= 3 V
AD7466/AD7467/AD7468
Rev. C | Page 9 of 28
TIMING SPECIFICATIONS
For all devices, V
DD
= 1.6 V to 3.6 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input
signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.4 V.
Table 4.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
SCLK
3.4 MHz max Mark/space ratio for the SCLK input is 40/60 to 60/40.
10 kHz min 1.6 V ≤ V
DD
≤ 3 V; minimum f
SCLK
at which specifications are guaranteed.
20 kHz min V
DD
= 3.3 V; minimum f
SCLK
at which specifications are guaranteed.
150 kHz min V
DD
= 3.6 V; minimum f
SCLK
at which specifications are guaranteed.
t
CONVERT
16 × t
SCLK
AD7466.
12 × t
SCLK
AD7467.
10 × t
SCLK
AD7468.
Acquisition Time
Acquisition time/power-up time from power-down. See the
Terminology section.
The acquisition time is the time required for the part to acquire a full-scale step
input value within ±1 LSB or a 30 kHz ac input value within ±0.5 LSB.
780 ns max V
DD
= 1.6 V.
640 ns max 1.8 V ≤ V
DD
≤ 3.6 V.
t
QUIET
10 ns min
Minimum quiet time required between bus relinquish and the start of the next
conversion.
t
1
10 ns min
Minimum
CS pulse width.
t
2
55 ns min
CS to SCLK setup time. If V
DD
= 1.6 V and f
SCLK
= 3.4 MHz, t
2
has to be 192 ns
minimum in order to meet the maximum figure for the acquisition time.
t
3
55 ns max
Delay from
CS until SDATA is three-state disabled. Measured with the load circuit
in Figure 2 and defined as the time required for the output to cross the V
IH
or V
IL
voltage.
t
4
140 ns max
Data access time after SCLK falling edge. Measured with the load circuit in
Figure 2
and defined as the time required for the output to cross the V
IH
or V
IL
voltage.
t
5
0.4 t
SCLK
ns min SCLK low pulse width.
t
6
0.4 t
SCLK
ns min SCLK high pulse width.
t
7
10 ns min
SCLK to data valid hold time. Measured with the load circuit in
Figure 2 and
defined as the time required for the output to cross the V
IH
or V
IL
voltage.
t
8
60 ns max
SCLK falling edge to SDATA three-state. t
8
is derived from the measured time taken
by the data outputs to change 0.5 V when loaded with the circuit in
Figure 2. The
measured number is then extrapolated back to remove the effects of charging or
discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing
characteristics, is the true bus relinquish time of the part, and is independent of
the bus loading.
7 ns min SCLK falling edge to SDATA three-state.
200μAI
OL
200μAI
OH
1.4V
TO OUTPUT
PIN
C
L
50pF
02643-002
Figure 2. Load Circuit for Digital Output Timing Specifications
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

AD7468BRTZ-REEL7

Mfr. #:
Buy AD7468BRTZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 1.6V MicroPwr 8-Bit
Lifecycle:
New from this manufacturer.
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