DATASHEET
9SQL4954 NOVEMBER 4, 2016 1 ©2016 Integrated Device Technology, Inc.
4-output CK420BQ Derivative 9SQL4954
Description
The 9SQL4954 is a member of IDT's 'Lite' family of server
clocks. It generates 4 100MHz outputs that exceed the
requirements of the CK420BQ CPU/SRC clocks. Each output
has its own OE# pin for clock management and supports 2
different spread spectrum levels in addition to spread off. It
also provides a copy of the 25MHz internal XO. The
9SQL4954 supports PCIe Common Clock (CC) and
Independent Reference Clock (IR) architectures.
Recommended Application
PCIe Gen1, Gen2, Gen3, Gen4 Server Clock
Output Features
4 -100MHz Low-power HCSL (LP-HCSL) CPU/SRC pairs
Integrated terminations for 85 Zout
1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
BCLK outputs:
Cycle-to-cycle jitter <50ps
Output-to-output skew <50ps
PCIe Gen1, Gen2, Gen3, Gen4 CC compliant
PCIe Gen2, Gen3 IR compliant
QPI/UPI compliant
SAS12G compliant (SSC off)
12k-20M phase jitter <2ps rms (SSC off)
REF output:
Phase jitter <200fs rms (SSC off)
±50ppm frequency accuracy on all clocks
Features/Benefits
Direct connection to 85 transmission lines; saves 16
resistors and 27mm
2
compared to standard HCSL
142mW typical power consumption; eases thermal
concerns @ 1/10 the power of CK420BQ
Contains default configuration; SMBus interface not
required for device operation
OE# pins; support BCLK power management
25MHz input frequency; standard crystal frequency
25MHz REF output; eliminates XO from boar
Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF
outputs; minimize EMI and phase jitter for each application
BCLK outputs blocked until PLL is locked; clean system
start-up
Two selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 32-pin 5x5mm VFQFPN; minimal board
space
Block Diagram
y
XIN/CLKIN_25
X2
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
REF
vOE(3:0)#
SCLK_3.3
vSADR
BCLK0
4
SSC
Capable
PLL
Control
Logic
BCLK3
BCLK2
BCLK1
4-OUTPUT CK420BQ DERIVATIVE 2 NOVEMBER 4, 2016
9SQL4954 DATASHEET
Pin Configuration
SMBus Address Selection Table
Power Management Table
Power Connections
vSS_EN_tri
^CKPWRGD_PD#
GND
vOE3#
BCLK3#
BCLK3
GND
VDDO3.3
32 31 30 29 28 27 26 25
GNDXTAL 1
24
vOE2#
XIN/CLKIN_25 2
23
BCLK2#
X2 3
22
BCLK2
VDDXTAL3.3 4
21
VDDA3.3
VDDREF3.3 5
20
GNDA
vSADR/REF3.3 6
19
BCLK1#
GNDREF
7
18
BCLK1
GNDDIG
817vOE1#
9 10111213141516
VDDDIG3.3
SCLK_3.3
SDATA_3.3
vOE0#
BCLK0
BCLK0#
GND
VDDO3.3
9SQL4954
connect
epad to GND
32-pin VFQFPN, 5x5 mm, 0.5mm pitch
v prefix indicates internal 120KOhm pull down resistor
^ prefix indicates internal 120KOhm pull up resistor
SADR Address
0 1101000
1 1101010
State of SADR on first application
of CKPWRGD_PD#
+ Read/Write Bit
x
x
True O/P Comp. O/P
0XX
Low
1
Low
1
Hi-Z
2
1 1 0 Running Running Running
111
Disabled
1
Disabled
1
Running
10X
Disabled
1
Disabled
1
Disabled
4
1. The output state is set by B11[1:0] (Low/Low default)
3. Input polarities defined at default SMBus values.
4. See SMBus description for Byte 3, bit 4
2. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is disabled unless Byte3[5]=1, in which case REF is
running..
CKPW RGD_PD#
SMBus
OE bit
OEx#
Pin
BCLKx
REF
Pin Number
VDD GND
41
57
98, 30
16, 25 15, 26, 33
21 20 PLL Analog
REF Output
Description
XTAL Analo
g
Di
g
ital Power
BCLK outputs
NOVEMBER 4, 2016 3 4-OUTPUT CK420BQ DERIVATIVE
9SQL4954 DATASHEET
Pin Descriptions

9SQL4954BNLGI

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 4 O/P CK420BQ Lite OEM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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